3e34a52db5
stm32/common: Created a Meson build system for common part of STM32 targets
2025-07-12 10:32:11 -07:00
0caee68805
cm3: Created a Meson build system for the CM3 component
2025-07-12 10:32:11 -07:00
81921a4839
ethernet: Created a Meson build system for the Ethernet component
2025-07-12 10:32:11 -07:00
41e99dc469
usb: Created a Meson build system for the USB component
2025-07-12 10:32:11 -07:00
cb1fe86008
stm32: usart_common_all: Implement usart_get_baudrate
...
* Handle OVER8 when set, as 2x clock
* Handle LPUART specially, as 256x clock, without overflowing uint32_t
2025-07-12 13:39:32 +01:00
9059ec1a42
lm4f/uart: Implement uart_get_baudrate
2025-07-12 13:39:32 +01:00
754dac7686
usb:msc: use new email for contributor
2025-07-11 21:13:13 -07:00
a7632df7f4
iwdg: START and UNLOCK values before polling Busy
...
With code that uses IWDG and these operations:
- user code initializes iwdg
- user code jumps to USB-DFU
- USB host triggers a USB exit (e.g. after reflashing, or even just a
dummy dfu-util Reset/Exit command)
- user code will hang in iwdg_prescaler_busy() called from
iwdg_set_period_ms()
2025-07-11 21:05:58 -07:00
cc3a1e8a98
Added timer support
2025-07-11 20:31:43 -07:00
ab284959f3
Added Exti support
2025-07-11 20:31:43 -07:00
3f5e250f42
Added iwdg support + early wakeup
2025-07-11 20:31:43 -07:00
edbb8ed7e3
Added I2C stm32u5_support
...
Tested I2C master mode on 16MHz HSI
2025-07-11 20:31:43 -07:00
e6632cda77
Added support for USARTs and clock setup
...
Tested:
- USART2 Rx/Tx with:
- In 8N1 115200
- With sysclk set as HSI and default setup
- With all clk input types for USART2
2025-07-11 20:31:43 -07:00
730cfec66c
Add IRQ handlers and missing Makefile FP flags
2025-07-11 20:31:43 -07:00
4d442299fe
Add irq/memorymap/rcc
2025-07-11 20:31:43 -07:00
6bcdb117b7
Added device family to linker generator
2025-07-11 20:31:43 -07:00
48cc714746
stm32/h7: Implemented a function for getting back a bank's status flags
2025-07-11 20:26:35 -07:00
2a6059540d
stm32/h7: Implemented support for enabling the RTC clock source and peripheral
2025-07-11 20:26:35 -07:00
bf7929b723
stm32/h7: Fixed the consistency of the function definitions in the RCC implementation
2025-07-11 20:26:35 -07:00
26cb7f0ded
stm32/h7: Implemented support for the LSI clock source
2025-07-11 20:26:35 -07:00
7047e3d01c
stm32/h7: Implemented support for DMAMUX1
2025-07-11 20:26:35 -07:00
c0cd79359d
stm32/h7: Enabled the main DMA controllers
2025-07-11 20:26:35 -07:00
9087802ce7
stm32/h7: Enabled the CRC32 generator peripheral
2025-07-11 20:26:35 -07:00
94411df91f
stm32/common: Implemented oversampling control support for the F2/F4 parts
2025-07-11 20:26:35 -07:00
03a884bcca
stm32/h7: Fixed an issue with how the RCC implementation decides which VCO to use in a given PLL
2025-07-11 20:26:35 -07:00
0685d162df
stm32/h7: Fixed the accuracy of all the RCC clock frequency calculations as the Hz->MHz conversion was discarding too much information
2025-07-11 20:26:35 -07:00
10acaab08b
stm32/h7: Fixed a couple of issues with the clock selector handling for the USARTs and peripherals
2025-07-11 20:26:35 -07:00
74ffe55dc5
stm32/h7: Fixed an accuracy issue in the PLL clock input frequency calculation that resulted in all the follow-on calculations being way off in value
2025-07-11 20:26:35 -07:00
80ffd05933
stm32/h7: Fixed an issue with the naming of the D2CCIP2R selector constant for some of the USARTs
2025-07-11 20:26:35 -07:00
2d15b12ff2
stm32/common: Implement handling for setting the baud rate correctly when in 8x oversampling mode
2025-07-11 20:26:35 -07:00
9480f493b9
stm32/common: Implement support for DE and changing the oversampling mode
2025-07-11 20:26:35 -07:00
7e4a6334a1
usb/dwc: Cleanup in the setup interrupt handling and IN endpoint handling
2025-07-11 20:26:35 -07:00
b622d4b555
stm32/h7: Implemented handling for bringing up the 3.3V USB voltage supply
2025-07-11 20:26:35 -07:00
c3d972632a
usb/dwc: Fixed how the endpoints were configured and brought up during endpoint setup for the H7
2025-07-11 20:26:35 -07:00
484bfee238
usb/dwc: const-correctness improvements
2025-07-11 20:26:35 -07:00
adb4f73125
usb/dwc: Fixed a whole lot of constants issues in the common header
2025-07-11 20:26:35 -07:00
6b4592c82d
usb/dwc: Corrected how interrupts are handled for the H7's DWC2 so that setup and out packets are properly acknowledged
2025-07-11 20:26:35 -07:00
5e6c423100
usb/dwc: Corrected how packets are read and unloaded from the DWC2 FIFOs on the H7
2025-07-11 20:26:35 -07:00
d9779685ae
usb/dwc: Further implementation cleanup to fix integer conversions issues
2025-07-11 20:26:35 -07:00
7851b5e4a5
usb/dwc: Cleaned up in the endpoint setup implementation to improve const-ness
2025-07-11 20:26:35 -07:00
714e7b1c91
usb/dwc: Corrected how packets are written and loaded to the DWC2 FIFOs on the H7
2025-07-11 20:26:35 -07:00
7da573f9eb
usb/dwc: Fixed some issues with how interrupts were being handled for the H7's DWC2 variant
2025-07-11 20:26:35 -07:00
76ba8900e3
usb/dwc: Fixed how the control endpoints are configured when built for STM32H7
2025-07-11 20:26:35 -07:00
22ef380fbf
usb: Fixed up the number of endpoints defined in the control structures
2025-07-11 20:26:35 -07:00
e135b9000d
usb: Cleaned up a little in the control endpoint implementation
2025-07-11 20:26:35 -07:00
61ed913de9
usb/dwc: Fixed the endpoint count being wrong on some devices as the DWC does not have a fixed endpoint count
2025-07-11 20:26:35 -07:00
972d408ba5
stm32/h7: Implemented support changing the clock routed to the USB peripherals in the RCC
2025-07-11 20:26:35 -07:00
2b6eb047e0
stm32/h7: Implemented support for the HSI48
2025-07-11 20:26:35 -07:00
9f8ce70771
stm32/h7: Enabled support for the CRS controller
2025-07-11 20:26:35 -07:00
cdd8f2adac
stm32/h7: Implemented support for the Flash controller having untangled the previous pretending it was the F2/F4 controller mess
2025-07-11 20:26:35 -07:00
dragonmux