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usb: Fixed up the number of endpoints defined in the control structures

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This commit is contained in:
dragonmux
2024-04-17 18:43:21 +01:00
committed by Piotr Esden-Tempski
parent e135b9000d
commit 22ef380fbf
3 changed files with 14 additions and 13 deletions
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3
lib/usb/usb.c
View File

@@ -67,8 +67,7 @@ usbd_device *usbd_init(const usbd_driver *driver,
usbd_dev->user_callback_ctr[0][USB_TRANSACTION_IN] =
_usbd_control_in;
int i;
for (i = 0; i < MAX_USER_SET_CONFIG_CALLBACK; i++) {
for (size_t i = 0; i < MAX_USER_SET_CONFIG_CALLBACK; i++) {
usbd_dev->user_callback_set_config[i] = NULL;
}

13
lib/usb/usb_dwc_common.c
View File

@@ -31,13 +31,6 @@
#define dev_base_address (usbd_dev->driver->base_address)
#define REBASE(x) MMIO32((x) + (dev_base_address))
/* The max number of endpoints is core-dependant - for the F4 it's 4, for the H7 it's 8 */
#if defined(STM32H7)
#define DWC_ENDPOINT_COUNT 8U
#else
#define DWC_ENDPOINT_COUNT 4U
#endif
void dwc_set_address(usbd_device *usbd_dev, uint8_t addr)
{
REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_DCFG_DAD) | (addr << 4);
@@ -122,7 +115,7 @@ void dwc_endpoints_reset(usbd_device *usbd_dev)
usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0;
/* Disable any currently active endpoints */
for (size_t i = 1; i < DWC_ENDPOINT_COUNT; i++) {
for (size_t i = 1; i < ENDPOINT_COUNT; i++) {
if (REBASE(OTG_DOEPCTL(i)) & OTG_DOEPCTL0_EPENA) {
REBASE(OTG_DOEPCTL(i)) |= OTG_DOEPCTL0_EPDIS;
}
@@ -340,8 +333,10 @@ void dwc_poll(usbd_device *usbd_dev)
/*
* There is no global interrupt flag for transmit complete.
* The XFRC bit must be checked in each OTG_DIEPINT(x).
*
* Iterate over the IN endpoints, triggering any post-transmit actions.
*/
for (size_t i = 0; i < DWC_ENDPOINT_COUNT; i++) { /* Iterate over endpoints. */
for (size_t i = 0; i < ENDPOINT_COUNT; i++) {
if (REBASE(OTG_DIEPINT(i)) & OTG_DIEPINTX_XFRC) {
/* Transfer complete. */
if (usbd_dev->user_callback_ctr[i]

11
lib/usb/usb_private.h
View File

@@ -43,6 +43,13 @@ LGPL License Terms @ref lgpl_license
#define MIN(a, b) ((a) < (b) ? (a) : (b))
/* The max number of endpoints is core-dependant - for the F4 it's 4, for the H7 it's 8 */
#if defined(STM32H7)
#define ENDPOINT_COUNT 8U
#else
#define ENDPOINT_COUNT 4U
#endif
/** Internal collection of device information. */
struct _usbd_device {
const struct usb_device_descriptor *desc;
@@ -105,12 +112,12 @@ struct _usbd_device {
uint16_t fifo_mem_top;
uint16_t fifo_mem_top_ep0;
uint8_t force_nak[4];
uint8_t force_nak[ENDPOINT_COUNT];
/*
* We keep a backup copy of the out endpoint size registers to restore
* them after a transaction.
*/
uint32_t doeptsiz[4];
uint32_t doeptsiz[ENDPOINT_COUNT];
/*
* Received packet size for each endpoint. This is assigned in
* stm32f107_poll() which reads the packet status push register GRXSTSP