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stm32/h7: Fixed an issue with the naming of the D2CCIP2R selector constant for some of the USARTs

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dragonmux
2024-04-26 10:50:15 +01:00
committed by Piotr Esden-Tempski
parent 2d15b12ff2
commit 80ffd05933
2 changed files with 4 additions and 4 deletions
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2
include/libopencm3/stm32/h7/rcc.h
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@@ -414,7 +414,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_D2CCIP2R_I2C123SEL_SHIFT 12U
#define RCC_D2CCIP2R_RNGSEL_MASK 0x3U
#define RCC_D2CCIP2R_RNGSEL_SHIFT 8U
#define RCC_D2CCIP2R_USART16SEL_SHIFT 3U
#define RCC_D2CCIP2R_USART16910SEL_SHIFT 3U
#define RCC_D2CCIP2R_USART234578SEL_SHIFT 0U
#define RCC_D2CCIP2R_USARTSEL_MASK 7U

6
lib/stm32/h7/rcc.c
View File

@@ -272,7 +272,7 @@ uint32_t rcc_get_usart_clk_freq(uint32_t usart)
uint32_t clksel, pclk;
if (usart == USART1_BASE || usart == USART6_BASE) {
pclk = rcc_clock_tree.per.pclk2_mhz * HZ_PER_MHZ;;
clksel = (RCC_D2CCIP2R >> RCC_D2CCIP2R_USART16SEL_SHIFT) & RCC_D2CCIP2R_USARTSEL_MASK;
clksel = (RCC_D2CCIP2R >> RCC_D2CCIP2R_USART16910SEL_SHIFT) & RCC_D2CCIP2R_USARTSEL_MASK;
} else {
pclk = rcc_clock_tree.per.pclk1_mhz * HZ_PER_MHZ;
clksel = (RCC_D2CCIP2R >> RCC_D2CCIP2R_USART234578SEL_SHIFT) & RCC_D2CCIP2R_USARTSEL_MASK;
@@ -404,8 +404,8 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) {
case UART9_BASE:
case USART10_BASE:
reg = &RCC_D2CCIP2R;
mask = RCC_D2CCIP2R_USARTSEL_MASK << RCC_D2CCIP2R_USART16SEL_SHIFT;
val = sel << RCC_D2CCIP2R_USART16SEL_SHIFT;
mask = RCC_D2CCIP2R_USARTSEL_MASK << RCC_D2CCIP2R_USART16910SEL_SHIFT;
val = sel << RCC_D2CCIP2R_USART16910SEL_SHIFT;
break;
case USART2_BASE:
case USART3_BASE: