- rcc_get_i2c_clk_freq: Add support by taking RCC_CCIPR2 into account for I2C4.
- rcc_get_timer_clk_freq: Add support for LP timers
- rcc_get_usart_clk_freq: Fix APB freq used for LPUART1 and UART1, respectively.
This commit adds support for NRF52 TWI Master mode and slightly extends
existing I2C API. This is a breaking change, while mode selection needs to be
done during enabling I2C. There is one additional breaking change done because:
1) Unicore MX API design was PITA for writes
2) It is incompatible with EasyDMA
I strongly apologize to all two users who might be affected by this change.
* added: Linker script adds support for RAM4 and RAM5 memory regions, so
that those are usable by code. This also fixes the fact that RAM4 was
declared, but inaccessible previously
* changed: RAM1 is renamed to RAM2, shifting numbering of all regions.
This is done in order to be in line with other STM32 definitions,
similarly ROM1 became ROM2.
by making it vaguer. These days, there's extra timers that support the
BDTR register, so the simple "advanced" timer description is no longer
sufficiently clear. You have to check your particular reference manual.
Fixes: https://github.com/libopencm3/libopencm3/issues/1378
Presumably copy/paste error in original submission.
Verified in RM0440rev1 and rev5.
Fixes: c26eab251
Reported-by: qyx on the internet
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
* merged: nrf tree from unicore-mx
* fixed: small changes to make merged code play with rest of locm3 again
* added: linker script generator defines for nRF51/52 stubs
* added: doxygen support
This removes code and changes names and styles where relevant to be more
inline with normal libopencm3.
NRF52x library is built for hardfloat, M4F by default. The M4 no float
variants are less common, and if needed, the library can be built
manually for those variants. Unless some very common boards show up
using those parts, we don't need an extra library build.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Tested-by: Karl Palsson <karlp@tweak.net.au>
F411 parts, found on "black pill" boards support 100MHz operation,
but only 96MHz with USB. Provide default clock structures for this
common max speed.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Fix the bug that the iwdg counter is not refreshed after the configurationis complete, if this counter is not refreshed after the configuration is completed, the first iwdg counting period will be as long as 26 seconds.
Fixes: https://github.com/libopencm3/libopencm3/pull/1333
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Nothing extra needed to be defined here - this might've just been missed
when adding STM32G0 support. Tested and works well on an STM32G051. Registers
in `stm32/common/dac_common_v1.h` match the STM32G0x1 reference manual.
Fix FDCAN FIFO acknowledge register definition to make it correct for H7
MCUs. Previous definition contained hardcoded offset instead of using
MCU-specific macro.
Fix incorrect decoding of buffer element size. During decoding, value
returned was erratically set to 7 instead of setting 4th LSB. Buffer
element size was then always reported as 15 bytes.
Fix incorrect way of acknowledging FIFO processing. Old code ORed old
value of register with index of FIFO buffer just processed, which
generated invalid value for acknowledge. This caused FIFO to repeatedly
returning same content. Both fdcan_receive() and fdcan_release_fifo were
affected.
Fix the bug where certain functions were returning meaningful return
and/or error code, where positive values of error codes were interfering
with meaningful return value. Error codes now have negative values as it
was originally intended but never implemented.
