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stm32f4: rcc: F411: support Full speed with usb.

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F411 parts, found on "black pill" boards support 100MHz operation,
but only 96MHz with USB.  Provide default clock structures for this
common max speed.

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
Tim Børresen
2021-09-25 12:54:50 +02:00
committed by Karl Palsson
parent 6763681c26
commit f5813a547a
2 changed files with 81 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
include/libopencm3/stm32/f4/rcc.h
View File

@@ -796,6 +796,7 @@ extern uint32_t rcc_apb2_frequency;
enum rcc_clock_3v3 {
RCC_CLOCK_3V3_84MHZ,
RCC_CLOCK_3V3_96MHZ,
RCC_CLOCK_3V3_168MHZ,
RCC_CLOCK_3V3_180MHZ,
RCC_CLOCK_3V3_END

80
lib/stm32/f4/rcc.c
View File

@@ -67,6 +67,22 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 96MHz */
.pllm = 8,
.plln = 96,
.pllp = 2,
.pllq = 4,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_2,
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 96000000,
.apb1_frequency = 48000000,
.apb2_frequency = 96000000
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
@@ -121,6 +137,22 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 96MHz */
.pllm = 4,
.plln = 96,
.pllp = 2,
.pllq = 4,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_2,
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 96000000,
.apb1_frequency = 48000000,
.apb2_frequency = 96000000
},
{ /* 168MHz */
.pllm = 8,
.plln = 336,
@@ -175,6 +207,22 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 96MHz */
.pllm = 6,
.plln = 96,
.pllp = 2,
.pllq = 4,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_2,
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 96000000,
.apb1_frequency = 48000000,
.apb2_frequency = 96000000
},
{ /* 168MHz */
.pllm = 12,
.plln = 336,
@@ -229,6 +277,22 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 96MHz */
.pllm = 8,
.plln = 96,
.pllp = 2,
.pllq = 4,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_2,
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 96000000,
.apb1_frequency = 48000000,
.apb2_frequency = 96000000
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
@@ -283,6 +347,22 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 96MHz */
.pllm = 25,
.plln = 192,
.pllp = 2,
.pllq = 4,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_2,
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 96000000,
.apb1_frequency = 48000000,
.apb2_frequency = 96000000
},
{ /* 168MHz */
.pllm = 25,
.plln = 336,