dragonmux
4cbdba2d31
stm32/f1: Created a Meson build system for the STM32F1 series support
2025-07-12 10:32:11 -07:00
dragonmux
3e34a52db5
stm32/common: Created a Meson build system for common part of STM32 targets
2025-07-12 10:32:11 -07:00
dragonmux
0caee68805
cm3: Created a Meson build system for the CM3 component
2025-07-12 10:32:11 -07:00
dragonmux
81921a4839
ethernet: Created a Meson build system for the Ethernet component
2025-07-12 10:32:11 -07:00
dragonmux
41e99dc469
usb: Created a Meson build system for the USB component
2025-07-12 10:32:11 -07:00
ALTracer
cb1fe86008
stm32: usart_common_all: Implement usart_get_baudrate
...
* Handle OVER8 when set, as 2x clock
* Handle LPUART specially, as 256x clock, without overflowing uint32_t
2025-07-12 13:39:32 +01:00
ALTracer
9059ec1a42
lm4f/uart: Implement uart_get_baudrate
2025-07-12 13:39:32 +01:00
Pavol Rusnak
754dac7686
usb:msc: use new email for contributor
2025-07-11 21:13:13 -07:00
fenugrec
a7632df7f4
iwdg: START and UNLOCK values before polling Busy
...
With code that uses IWDG and these operations:
- user code initializes iwdg
- user code jumps to USB-DFU
- USB host triggers a USB exit (e.g. after reflashing, or even just a
dummy dfu-util Reset/Exit command)
- user code will hang in iwdg_prescaler_busy() called from
iwdg_set_period_ms()
2025-07-11 21:05:58 -07:00
Piotr Esden-Tempski
9624f92d81
CI: Remove travis as it is bitrotten.
...
It needs to be replaced with GHA anyways.
2025-07-11 20:58:25 -07:00
Piotr Esden-Tempski
e3f9a612a8
doc: Update link to the community chat.
...
The community chat is now on the 1BitSquared Discord.
2025-07-11 20:58:25 -07:00
Mateusz Myalski
cc3a1e8a98
Added timer support
2025-07-11 20:31:43 -07:00
Mateusz Myalski
ab284959f3
Added Exti support
2025-07-11 20:31:43 -07:00
Mateusz Myalski
3f5e250f42
Added iwdg support + early wakeup
2025-07-11 20:31:43 -07:00
Mateusz Myalski
edbb8ed7e3
Added I2C stm32u5_support
...
Tested I2C master mode on 16MHz HSI
2025-07-11 20:31:43 -07:00
Mateusz Myalski
e6632cda77
Added support for USARTs and clock setup
...
Tested:
- USART2 Rx/Tx with:
- In 8N1 115200
- With sysclk set as HSI and default setup
- With all clk input types for USART2
2025-07-11 20:31:43 -07:00
Mateusz Myalski
f1df03ce9e
Add length for RAM3 and RAM4
2025-07-11 20:31:43 -07:00
Mateusz Myalski
730cfec66c
Add IRQ handlers and missing Makefile FP flags
2025-07-11 20:31:43 -07:00
Mateusz Myalski
f05b5abdab
Add coresponding documentation entry
2025-07-11 20:31:43 -07:00
Mateusz Myalski
4d442299fe
Add irq/memorymap/rcc
2025-07-11 20:31:43 -07:00
Mateusz Myalski
3324dd4069
Revert invalid change in gd32
2025-07-11 20:31:43 -07:00
Mateusz Myalski
90cfa21a05
Added minimal memory map gpi and rcc to blink LED
2025-07-11 20:31:43 -07:00
Mateusz Myalski
236426f0ff
Added minimal memory map
2025-07-11 20:31:43 -07:00
Mateusz Myalski
6bcdb117b7
Added device family to linker generator
2025-07-11 20:31:43 -07:00
Mateusz Myalski
b7fcf025e7
Added stm32u5 library target
2025-07-11 20:31:43 -07:00
dragonmux
48cc714746
stm32/h7: Implemented a function for getting back a bank's status flags
2025-07-11 20:26:35 -07:00
dragonmux
3a1b9861c7
stm32/h7: Added a definition for the "NULL" DMAMUX request source ID
2025-07-11 20:26:35 -07:00
dragonmux
79dfe1c284
stm32/h7: Fixed all the DMAMUX1 channel values being off-by-one due to a rogue - 1 in the DMAMUX_CxCR() macro
2025-07-11 20:26:35 -07:00
dragonmux
38523d5878
cm3/common: Fixed the bit macros doing bad things with signed bit shifting
2025-07-11 20:26:35 -07:00
dragonmux
2a6059540d
stm32/h7: Implemented support for enabling the RTC clock source and peripheral
2025-07-11 20:26:35 -07:00
dragonmux
bf7929b723
stm32/h7: Fixed the consistency of the function definitions in the RCC implementation
2025-07-11 20:26:35 -07:00
dragonmux
8268fb2e29
stm32/h7: Added some missing decls for the USB clock selections
2025-07-11 20:26:35 -07:00
dragonmux
26cb7f0ded
stm32/h7: Implemented support for the LSI clock source
2025-07-11 20:26:35 -07:00
dragonmux
683c35de54
stm32/common: Fixed a boat load of signed bit manipulation issues
2025-07-11 20:26:35 -07:00
dragonmux
94247aedda
stm32/h7: Enabled support for the RTC
2025-07-11 20:26:35 -07:00
dragonmux
777dd14a7a
stm32/h7: Added some missing definitions for the PWR_CPUCR
2025-07-11 20:26:35 -07:00
dragonmux
7047e3d01c
stm32/h7: Implemented support for DMAMUX1
2025-07-11 20:26:35 -07:00
dragonmux
c0cd79359d
stm32/h7: Enabled the main DMA controllers
2025-07-11 20:26:35 -07:00
dragonmux
9087802ce7
stm32/h7: Enabled the CRC32 generator peripheral
2025-07-11 20:26:35 -07:00
dragonmux
c13dd75d55
stm32/common: Fixed some of the Flash headers defining constants in UB ways
2025-07-11 20:26:35 -07:00
dragonmux
94411df91f
stm32/common: Implemented oversampling control support for the F2/F4 parts
2025-07-11 20:26:35 -07:00
dragonmux
03a884bcca
stm32/h7: Fixed an issue with how the RCC implementation decides which VCO to use in a given PLL
2025-07-11 20:26:35 -07:00
dragonmux
0685d162df
stm32/h7: Fixed the accuracy of all the RCC clock frequency calculations as the Hz->MHz conversion was discarding too much information
2025-07-11 20:26:35 -07:00
dragonmux
6031fd8007
stm32/h7: Added a missing Flash ACR WRHF value
2025-07-11 20:26:35 -07:00
dragonmux
c5825de272
stm32/h7: Fixed some signed-unsigned issues in the RCC header
2025-07-11 20:26:35 -07:00
dragonmux
10acaab08b
stm32/h7: Fixed a couple of issues with the clock selector handling for the USARTs and peripherals
2025-07-11 20:26:35 -07:00
dragonmux
74ffe55dc5
stm32/h7: Fixed an accuracy issue in the PLL clock input frequency calculation that resulted in all the follow-on calculations being way off in value
2025-07-11 20:26:35 -07:00
dragonmux
80ffd05933
stm32/h7: Fixed an issue with the naming of the D2CCIP2R selector constant for some of the USARTs
2025-07-11 20:26:35 -07:00
dragonmux
2d15b12ff2
stm32/common: Implement handling for setting the baud rate correctly when in 8x oversampling mode
2025-07-11 20:26:35 -07:00
dragonmux
9480f493b9
stm32/common: Implement support for DE and changing the oversampling mode
2025-07-11 20:26:35 -07:00
