Mateusz Myalski
3324dd4069
Revert invalid change in gd32
2025-07-11 20:31:43 -07:00
Mateusz Myalski
90cfa21a05
Added minimal memory map gpi and rcc to blink LED
2025-07-11 20:31:43 -07:00
Mateusz Myalski
236426f0ff
Added minimal memory map
2025-07-11 20:31:43 -07:00
Mateusz Myalski
6bcdb117b7
Added device family to linker generator
2025-07-11 20:31:43 -07:00
dragonmux
48cc714746
stm32/h7: Implemented a function for getting back a bank's status flags
2025-07-11 20:26:35 -07:00
dragonmux
3a1b9861c7
stm32/h7: Added a definition for the "NULL" DMAMUX request source ID
2025-07-11 20:26:35 -07:00
dragonmux
79dfe1c284
stm32/h7: Fixed all the DMAMUX1 channel values being off-by-one due to a rogue - 1 in the DMAMUX_CxCR() macro
2025-07-11 20:26:35 -07:00
dragonmux
38523d5878
cm3/common: Fixed the bit macros doing bad things with signed bit shifting
2025-07-11 20:26:35 -07:00
dragonmux
2a6059540d
stm32/h7: Implemented support for enabling the RTC clock source and peripheral
2025-07-11 20:26:35 -07:00
dragonmux
8268fb2e29
stm32/h7: Added some missing decls for the USB clock selections
2025-07-11 20:26:35 -07:00
dragonmux
26cb7f0ded
stm32/h7: Implemented support for the LSI clock source
2025-07-11 20:26:35 -07:00
dragonmux
683c35de54
stm32/common: Fixed a boat load of signed bit manipulation issues
2025-07-11 20:26:35 -07:00
dragonmux
94247aedda
stm32/h7: Enabled support for the RTC
2025-07-11 20:26:35 -07:00
dragonmux
777dd14a7a
stm32/h7: Added some missing definitions for the PWR_CPUCR
2025-07-11 20:26:35 -07:00
dragonmux
7047e3d01c
stm32/h7: Implemented support for DMAMUX1
2025-07-11 20:26:35 -07:00
dragonmux
c0cd79359d
stm32/h7: Enabled the main DMA controllers
2025-07-11 20:26:35 -07:00
dragonmux
9087802ce7
stm32/h7: Enabled the CRC32 generator peripheral
2025-07-11 20:26:35 -07:00
dragonmux
c13dd75d55
stm32/common: Fixed some of the Flash headers defining constants in UB ways
2025-07-11 20:26:35 -07:00
dragonmux
94411df91f
stm32/common: Implemented oversampling control support for the F2/F4 parts
2025-07-11 20:26:35 -07:00
dragonmux
6031fd8007
stm32/h7: Added a missing Flash ACR WRHF value
2025-07-11 20:26:35 -07:00
dragonmux
c5825de272
stm32/h7: Fixed some signed-unsigned issues in the RCC header
2025-07-11 20:26:35 -07:00
dragonmux
80ffd05933
stm32/h7: Fixed an issue with the naming of the D2CCIP2R selector constant for some of the USARTs
2025-07-11 20:26:35 -07:00
dragonmux
2d15b12ff2
stm32/common: Implement handling for setting the baud rate correctly when in 8x oversampling mode
2025-07-11 20:26:35 -07:00
dragonmux
9480f493b9
stm32/common: Implement support for DE and changing the oversampling mode
2025-07-11 20:26:35 -07:00
dragonmux
b622d4b555
stm32/h7: Implemented handling for bringing up the 3.3V USB voltage supply
2025-07-11 20:26:35 -07:00
dragonmux
c3d972632a
usb/dwc: Fixed how the endpoints were configured and brought up during endpoint setup for the H7
2025-07-11 20:26:35 -07:00
dragonmux
adb4f73125
usb/dwc: Fixed a whole lot of constants issues in the common header
2025-07-11 20:26:35 -07:00
dragonmux
cfd515e89d
usb/dwc: Made one more of the out EP's interrupt mask values available for use in the H7 bringup code
2025-07-11 20:26:35 -07:00
dragonmux
714e7b1c91
usb/dwc: Corrected how packets are written and loaded to the DWC2 FIFOs on the H7
2025-07-11 20:26:35 -07:00
dragonmux
7da573f9eb
usb/dwc: Fixed some issues with how interrupts were being handled for the H7's DWC2 variant
2025-07-11 20:26:35 -07:00
dragonmux
76ba8900e3
usb/dwc: Fixed how the control endpoints are configured when built for STM32H7
2025-07-11 20:26:35 -07:00
dragonmux
51351862b9
usb/dwc: Added some defines that were missing for the DWC2 in the STM32H7 parts
2025-07-11 20:26:35 -07:00
dragonmux
972d408ba5
stm32/h7: Implemented support changing the clock routed to the USB peripherals in the RCC
2025-07-11 20:26:35 -07:00
dragonmux
2b6eb047e0
stm32/h7: Implemented support for the HSI48
2025-07-11 20:26:35 -07:00
dragonmux
9f8ce70771
stm32/h7: Enabled support for the CRS controller
2025-07-11 20:26:35 -07:00
dragonmux
a603670266
stm32/h7: Implemented support for the RCC reset status register
2025-07-11 20:26:35 -07:00
dragonmux
cdd8f2adac
stm32/h7: Implemented support for the Flash controller having untangled the previous pretending it was the F2/F4 controller mess
2025-07-11 20:26:35 -07:00
dragonmux
ee418f1780
usb: Fixed the USB string descriptor internal type appearing and being defined for C++ code, the unsized array member is UB in C++
2025-07-11 20:26:35 -07:00
dragonmux
c31a239ae3
stm32/h7: Defined variant identification constants
2025-07-11 20:26:35 -07:00
dragonmux
7079ffdcac
stm32/h7: Defined the device electronic signature addresses foro the memory map
2025-07-11 20:26:35 -07:00
dragonmux
da0a6a9ce4
usb/dwc: Fixed some type conversions errors in the common header
2025-07-11 20:26:35 -07:00
dragonmux
24cdca8101
usb/dwc: Enable the STM32H7 in the DWC2 support
2025-07-11 20:26:35 -07:00
dragonmux
903720f6dc
stm32/h7: Added a couple of missing U(S)ART defines to the USART header
2025-07-11 20:26:35 -07:00
dragonmux
83e571db67
stm32/h7: Fixed the QuadSPI headers not working with multiple peripehrals
2025-07-11 20:26:35 -07:00
dragonmux
d294ebf746
stm32/h7: Added various missing peripherals to the RCC header
2025-07-11 20:26:35 -07:00
dragonmux
5baf6c9957
stm32/h7: Corrected the memory map, adding in base addresses for peripherals found on the value line parts
2025-07-11 20:26:35 -07:00
dragonmux
36326945c9
stm32/h7/rcc: Fixed a typo in one of the docs comments for the clocking configuration structure
2025-07-11 20:26:35 -07:00
blutack
bb152f3ab7
Enable fifos on G4
2025-07-11 19:28:40 -07:00
blutack
6778da3659
Add LPUART1 definition to usart.h for stm32g4x
...
Add LPUART1 definition for the STM32G4xx LPUART. It is possible to use LPUART1_BASE, but without the LPUART1 definition, usart_set_baudrate will calculate BRR incorrectly and the UART will not work due to an ifdef.
Tested and working @ 115200 on a NUCLEO-G474RE.
2025-07-11 19:28:40 -07:00
dragonmux
5864756482
stm32/timer: Exposed the new OC mode functions in the header
2025-07-11 19:15:56 -07:00
