stm32/h7: Fixed some signed-unsigned issues in the RCC header
This commit is contained in:
dragonmux
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
10acaab08b
commit
c5825de272
@@ -128,87 +128,87 @@ LGPL License Terms @ref lgpl_license
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* @ingroup rcc_registers
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@{*/
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/* MCO2: Microcontroller clock output 2 */
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#define RCC_CFGR_MCO2_MASK 0x7
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#define RCC_CFGR_MCO2_SHIFT 29
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#define RCC_CFGR_MCO2_SYSCLK 0x0
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#define RCC_CFGR_MCO2_PLL2 0x1
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#define RCC_CFGR_MCO2_HSE 0x2
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#define RCC_CFGR_MCO2_PLL1 0x3
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#define RCC_CFGR_MCO2_CSI 0x4
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#define RCC_CFGR_MCO2_LSI 0x5
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#define RCC_CFGR_MCO2_MASK 0x7U
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#define RCC_CFGR_MCO2_SHIFT 29U
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#define RCC_CFGR_MCO2_SYSCLK 0x0U
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#define RCC_CFGR_MCO2_PLL2 0x1U
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#define RCC_CFGR_MCO2_HSE 0x2U
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#define RCC_CFGR_MCO2_PLL1 0x3U
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#define RCC_CFGR_MCO2_CSI 0x4U
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#define RCC_CFGR_MCO2_LSI 0x5U
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/* MCO1/2PRE: MCO Prescalers */
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#define RCC_CFGR_MCOPRE_MASK 0xf
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#define RCC_CFGR_MCO2PRE_SHIFT 25
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#define RCC_CFGR_MCO1PRE_SHIFT 18
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#define RCC_CFGR_MCOPRE_DIV_NONE 0x0
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#define RCC_CFGR_MCOPRE_DIV_BYP 0x1
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#define RCC_CFGR_MCOPRE_DIV_2 0x2
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#define RCC_CFGR_MCOPRE_DIV_3 0x3
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#define RCC_CFGR_MCOPRE_DIV_4 0x4
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#define RCC_CFGR_MCOPRE_MASK 0xfU
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#define RCC_CFGR_MCO2PRE_SHIFT 25U
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#define RCC_CFGR_MCO1PRE_SHIFT 18U
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#define RCC_CFGR_MCOPRE_DIV_NONE 0x0U
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#define RCC_CFGR_MCOPRE_DIV_BYP 0x1U
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#define RCC_CFGR_MCOPRE_DIV_2 0x2U
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#define RCC_CFGR_MCOPRE_DIV_3 0x3U
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#define RCC_CFGR_MCOPRE_DIV_4 0x4U
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/* Note: MCOPRE_DIV can go from 1 - 15 */
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/* MCO1: Microcontroller clock output 1 */
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#define RCC_CFGR_MCO1_MASK 0x7
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#define RCC_CFGR_MCO1_SHIFT 22
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#define RCC_CFGR_MCO1_HSI 0x0
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#define RCC_CFGR_MCO1_LSE 0x1
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#define RCC_CFGR_MCO1_HSE 0x2
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#define RCC_CFGR_MCO1_PLL1 0x3
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#define RCC_CFGR_MCO1_HSI48 0x4
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#define RCC_CFGR_MCO1_MASK 0x7U
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#define RCC_CFGR_MCO1_SHIFT 22U
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#define RCC_CFGR_MCO1_HSI 0x0U
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#define RCC_CFGR_MCO1_LSE 0x1U
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#define RCC_CFGR_MCO1_HSE 0x2U
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#define RCC_CFGR_MCO1_PLL1 0x3U
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#define RCC_CFGR_MCO1_HSI48 0x4U
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#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT
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#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK
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/* RTCPRE: HSE division factor for RTC clock */
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#define RCC_CFGR_RTCPRE_SHIFT 8
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#define RCC_CFGR_RTCPRE_MASK 0x3f
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#define RCC_CFGR_RTCPRE_SHIFT 8U
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#define RCC_CFGR_RTCPRE_MASK 0x3fU
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/* SWS: System clock switch status */
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#define RCC_CFGR_SWS_SHIFT 3
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#define RCC_CFGR_SWS_MASK 0x7
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#define RCC_CFGR_SWS_HSI 0x0
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#define RCC_CFGR_SWS_CSI 0x1
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#define RCC_CFGR_SWS_HSE 0x2
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#define RCC_CFGR_SWS_PLL1 0x3
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#define RCC_CFGR_SWS_SHIFT 3U
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#define RCC_CFGR_SWS_MASK 0x7U
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#define RCC_CFGR_SWS_HSI 0x0U
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#define RCC_CFGR_SWS_CSI 0x1U
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#define RCC_CFGR_SWS_HSE 0x2U
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#define RCC_CFGR_SWS_PLL1 0x3U
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/* SW: System clock switch */
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#define RCC_CFGR_SW_SHIFT 0
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#define RCC_CFGR_SW_MASK 0x7
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#define RCC_CFGR_SW_HSI 0x0
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#define RCC_CFGR_SW_CSI 0x1
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#define RCC_CFGR_SW_HSE 0x2
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#define RCC_CFGR_SW_PLL1 0x3
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#define RCC_CFGR_SW_SHIFT 0U
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#define RCC_CFGR_SW_MASK 0x7U
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#define RCC_CFGR_SW_HSI 0x0U
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#define RCC_CFGR_SW_CSI 0x1U
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#define RCC_CFGR_SW_HSE 0x2U
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#define RCC_CFGR_SW_PLL1 0x3U
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/**@}*/
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/** @defgroup rcc_d1cfgr_values RCC_D1CFGR Values
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* @ingroup rcc_registers
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* @{*/
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#define RCC_D1CFGR_D1CPRE_BYP 0x0
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#define RCC_D1CFGR_D1CPRE_DIV2 0x8
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#define RCC_D1CFGR_D1CPRE_DIV4 0x9
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#define RCC_D1CFGR_D1CPRE_DIV8 0xA
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#define RCC_D1CFGR_D1CPRE_DIV16 0xB
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#define RCC_D1CFGR_D1CPRE_DIV64 0xC
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#define RCC_D1CFGR_D1CPRE_DIV128 0xD
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#define RCC_D1CFGR_D1CPRE_DIV256 0xE
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#define RCC_D1CFGR_D1CPRE_DIV512 0xF
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#define RCC_D1CFGR_D1PPRE_BYP 0x0
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#define RCC_D1CFGR_D1PPRE_DIV2 0x4
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#define RCC_D1CFGR_D1PPRE_DIV4 0x5
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#define RCC_D1CFGR_D1PPRE_DIV8 0x6
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#define RCC_D1CFGR_D1PPRE_DIV16 0x7
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#define RCC_D1CFGR_D1HPRE_BYP 0x0
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#define RCC_D1CFGR_D1HPRE_DIV2 0x8
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#define RCC_D1CFGR_D1HPRE_DIV4 0x9
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#define RCC_D1CFGR_D1HPRE_DIV8 0xA
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#define RCC_D1CFGR_D1HPRE_DIV16 0xB
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#define RCC_D1CFGR_D1HPRE_DIV64 0xC
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#define RCC_D1CFGR_D1HPRE_DIV128 0xD
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#define RCC_D1CFGR_D1HPRE_DIV256 0xE
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#define RCC_D1CFGR_D1HPRE_DIV512 0xF
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#define RCC_D1CFGR_D1CPRE_BYP 0x0U
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#define RCC_D1CFGR_D1CPRE_DIV2 0x8U
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#define RCC_D1CFGR_D1CPRE_DIV4 0x9U
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#define RCC_D1CFGR_D1CPRE_DIV8 0xAU
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#define RCC_D1CFGR_D1CPRE_DIV16 0xBU
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#define RCC_D1CFGR_D1CPRE_DIV64 0xCU
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#define RCC_D1CFGR_D1CPRE_DIV128 0xDU
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#define RCC_D1CFGR_D1CPRE_DIV256 0xEU
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#define RCC_D1CFGR_D1CPRE_DIV512 0xFU
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#define RCC_D1CFGR_D1PPRE_BYP 0x0U
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#define RCC_D1CFGR_D1PPRE_DIV2 0x4U
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#define RCC_D1CFGR_D1PPRE_DIV4 0x5U
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#define RCC_D1CFGR_D1PPRE_DIV8 0x6U
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#define RCC_D1CFGR_D1PPRE_DIV16 0x7U
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#define RCC_D1CFGR_D1HPRE_BYP 0x0U
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#define RCC_D1CFGR_D1HPRE_DIV2 0x8U
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#define RCC_D1CFGR_D1HPRE_DIV4 0x9U
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#define RCC_D1CFGR_D1HPRE_DIV8 0xAU
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#define RCC_D1CFGR_D1HPRE_DIV16 0xBU
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#define RCC_D1CFGR_D1HPRE_DIV64 0xCU
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#define RCC_D1CFGR_D1HPRE_DIV128 0xDU
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#define RCC_D1CFGR_D1HPRE_DIV256 0xEU
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#define RCC_D1CFGR_D1HPRE_DIV512 0xFU
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#define RCC_D1CFGR_D1CPRE_SHIFT 8
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#define RCC_D1CFGR_D1PPRE_SHIFT 4
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#define RCC_D1CFGR_D1CPRE_SHIFT 8U
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#define RCC_D1CFGR_D1PPRE_SHIFT 4U
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#define RCC_D1CFGR_D1CPRE(cpre) (cpre << RCC_D1CFGR_D1CPRE_SHIFT)
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#define RCC_D1CFGR_D1PPRE(ppre) (ppre << RCC_D1CFGR_D1PPRE_SHIFT)
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#define RCC_D1CFGR_D1HPRE(hpre) (hpre)
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@@ -217,14 +217,14 @@ LGPL License Terms @ref lgpl_license
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/** @defgroup rcc_d2cfgr_values RCC_D2CFGR Values
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* @ingroup rcc_registers
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* @{*/
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#define RCC_D2CFGR_D2PPRE_BYP 0x0
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#define RCC_D2CFGR_D2PPRE_DIV2 0x4
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#define RCC_D2CFGR_D2PPRE_DIV4 0x5
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#define RCC_D2CFGR_D2PPRE_DIV8 0x6
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#define RCC_D2CFGR_D2PPRE_DIV16 0x7
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#define RCC_D2CFGR_D2PPRE_BYP 0x0U
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#define RCC_D2CFGR_D2PPRE_DIV2 0x4U
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#define RCC_D2CFGR_D2PPRE_DIV4 0x5U
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#define RCC_D2CFGR_D2PPRE_DIV8 0x6U
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#define RCC_D2CFGR_D2PPRE_DIV16 0x7U
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#define RCC_D2CFGR_D2PPRE2_SHIFT 8
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#define RCC_D2CFGR_D2PPRE1_SHIFT 4
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#define RCC_D2CFGR_D2PPRE2_SHIFT 8U
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#define RCC_D2CFGR_D2PPRE1_SHIFT 4U
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#define RCC_D2CFGR_D2PPRE2(ppre) (ppre << RCC_D2CFGR_D2PPRE2_SHIFT)
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#define RCC_D2CFGR_D2PPRE1(ppre) (ppre << RCC_D2CFGR_D2PPRE1_SHIFT)
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/**@}*/
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@@ -232,29 +232,29 @@ LGPL License Terms @ref lgpl_license
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/** @defgroup rcc_d3cfgr_values RCC_D3CFGR Values
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* @ingroup rcc_registers
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* @{*/
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#define RCC_D3CFGR_D3PPRE_BYP 0x0
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#define RCC_D3CFGR_D3PPRE_DIV2 0x4
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#define RCC_D3CFGR_D3PPRE_DIV4 0x5
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#define RCC_D3CFGR_D3PPRE_DIV8 0x6
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#define RCC_D3CFGR_D3PPRE_DIV16 0x7
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#define RCC_D3CFGR_D3PPRE_SHIFT 4
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#define RCC_D3CFGR_D3PPRE_BYP 0x0U
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#define RCC_D3CFGR_D3PPRE_DIV2 0x4U
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#define RCC_D3CFGR_D3PPRE_DIV4 0x5U
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#define RCC_D3CFGR_D3PPRE_DIV8 0x6U
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#define RCC_D3CFGR_D3PPRE_DIV16 0x7U
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#define RCC_D3CFGR_D3PPRE_SHIFT 4U
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#define RCC_D3CFGR_D3PPRE(ppre) (ppre << RCC_D3CFGR_D3PPRE_SHIFT)
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/**@}*/
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/** @defgroup rcc_pllckselr_values RCC_PLLCKSELR Values
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* @ingroup rcc_registers
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* @{*/
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#define RCC_PLLCKSELR_PLLSRC_HSI 0x0
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#define RCC_PLLCKSELR_PLLSRC_CSI 0x1
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#define RCC_PLLCKSELR_PLLSRC_HSE 0x2
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#define RCC_PLLCKSELR_PLLSRC_NONE 0x3
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#define RCC_PLLCKSELR_DIVM_DIS 0
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#define RCC_PLLCKSELR_DIVM_BYP 1
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#define RCC_PLLCKSELR_DIVM_MASK 0x3f
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#define RCC_PLLCKSELR_PLLSRC_HSI 0x0U
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#define RCC_PLLCKSELR_PLLSRC_CSI 0x1U
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#define RCC_PLLCKSELR_PLLSRC_HSE 0x2U
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#define RCC_PLLCKSELR_PLLSRC_NONE 0x3U
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#define RCC_PLLCKSELR_DIVM_DIS 0U
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#define RCC_PLLCKSELR_DIVM_BYP 1U
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#define RCC_PLLCKSELR_DIVM_MASK 0x3fU
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#define RCC_PLLCKSELR_DIVM3_SHIFT 20
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#define RCC_PLLCKSELR_DIVM2_SHIFT 12
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#define RCC_PLLCKSELR_DIVM1_SHIFT 4
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#define RCC_PLLCKSELR_DIVM3_SHIFT 20U
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#define RCC_PLLCKSELR_DIVM2_SHIFT 12U
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#define RCC_PLLCKSELR_DIVM1_SHIFT 4U
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#define RCC_PLLCKSELR_DIVM3(n) ((n) << RCC_PLLCKSELR_DIVM3_SHIFT)
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#define RCC_PLLCKSELR_DIVM2(n) ((n) << RCC_PLLCKSELR_DIVM2_SHIFT)
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@@ -264,10 +264,10 @@ LGPL License Terms @ref lgpl_license
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/** @defgroup rcc_pllcfgr_values RCC_PLLCFGR Values
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* @ingroup rcc_registers
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* @{*/
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#define RCC_PLLCFGR_PLLRGE_1_2MHZ 0
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#define RCC_PLLCFGR_PLLRGE_2_4MHZ 1
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#define RCC_PLLCFGR_PLLRGE_4_8MHZ 2
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#define RCC_PLLCFGR_PLLRGE_8_16MHZ 3
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#define RCC_PLLCFGR_PLLRGE_1_2MHZ 0U
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#define RCC_PLLCFGR_PLLRGE_2_4MHZ 1U
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#define RCC_PLLCFGR_PLLRGE_4_8MHZ 2U
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#define RCC_PLLCFGR_PLLRGE_8_16MHZ 3U
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#define RCC_PLLCFGR_DIVR3EN BIT24
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#define RCC_PLLCFGR_DIVQ3EN BIT23
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@@ -278,16 +278,16 @@ LGPL License Terms @ref lgpl_license
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#define RCC_PLLCFGR_DIVR1EN BIT18
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#define RCC_PLLCFGR_DIVQ1EN BIT17
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#define RCC_PLLCFGR_DIVP1EN BIT16
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#define RCC_PLLCFGR_PLL3RGE_SHIFT 10
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#define RCC_PLLCFGR_PLL3VCO_WIDE 0 /* 192 - 836MHz base output. */
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#define RCC_PLLCFGR_PLL3RGE_SHIFT 10U
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#define RCC_PLLCFGR_PLL3VCO_WIDE 0U /* 192 - 836MHz base output. */
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#define RCC_PLLCFGR_PLL3VCO_MED BIT9 /* 150 - 420MHz base output. */
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#define RCC_PLLCFGR_PLL3FRACEN BIT8
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#define RCC_PLLCFGR_PLL2RGE_SHIFT 6
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#define RCC_PLLCFGR_PLL2VCO_WIDE 0 /* 192 - 836MHz base output. */
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#define RCC_PLLCFGR_PLL2RGE_SHIFT 6U
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#define RCC_PLLCFGR_PLL2VCO_WIDE 0U /* 192 - 836MHz base output. */
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#define RCC_PLLCFGR_PLL2VCO_MED BIT5 /* 150 - 420MHz base output. */
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#define RCC_PLLCFGR_PLL2FRACEN BIT4
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#define RCC_PLLCFGR_PLL1RGE_SHIFT 2
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#define RCC_PLLCFGR_PLL1VCO_WIDE 0 /* 192 - 836MHz base output. */
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#define RCC_PLLCFGR_PLL1RGE_SHIFT 2U
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#define RCC_PLLCFGR_PLL1VCO_WIDE 0U /* 192 - 836MHz base output. */
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#define RCC_PLLCFGR_PLL1VCO_MED BIT1 /* 150 - 420MHz base output. */
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#define RCC_PLLCFGR_PLL1FRACEN BIT0
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/**@}*/
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@@ -295,16 +295,16 @@ LGPL License Terms @ref lgpl_license
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/** @defgroup rcc_plldivr_values RCC_PLLnDIVR Values
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* @ingroup rcc_registers
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* @{*/
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#define RCC_PLLNDIVR_DIVR_SHIFT 24
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#define RCC_PLLNDIVR_DIVQ_SHIFT 16
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#define RCC_PLLNDIVR_DIVP_SHIFT 9
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#define RCC_PLLNDIVR_DIVN_SHIFT 0
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#define RCC_PLLNDIVR_DIVR_SHIFT 24U
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#define RCC_PLLNDIVR_DIVQ_SHIFT 16U
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#define RCC_PLLNDIVR_DIVP_SHIFT 9U
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#define RCC_PLLNDIVR_DIVN_SHIFT 0U
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/* Need to preserve reserved bits, so give easy mask shortcut. */
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#define RCC_PLLNDIVR_DIVR(n) (((n) - 1) << RCC_PLLNDIVR_DIVR_SHIFT)
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#define RCC_PLLNDIVR_DIVQ(n) (((n) - 1) << RCC_PLLNDIVR_DIVQ_SHIFT)
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#define RCC_PLLNDIVR_DIVP(n) (((n) - 1) << RCC_PLLNDIVR_DIVP_SHIFT)
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#define RCC_PLLNDIVR_DIVN(n) (((n) - 1) << RCC_PLLNDIVR_DIVN_SHIFT)
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#define RCC_PLLNDIVR_DIVR(n) (((n) - 1U) << RCC_PLLNDIVR_DIVR_SHIFT)
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#define RCC_PLLNDIVR_DIVQ(n) (((n) - 1U) << RCC_PLLNDIVR_DIVQ_SHIFT)
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#define RCC_PLLNDIVR_DIVP(n) (((n) - 1U) << RCC_PLLNDIVR_DIVP_SHIFT)
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#define RCC_PLLNDIVR_DIVN(n) (((n) - 1U) << RCC_PLLNDIVR_DIVN_SHIFT)
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/**@}*/
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/** @defgroup rcc_rsr_values RCC_RSR Values
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@@ -326,85 +326,85 @@ LGPL License Terms @ref lgpl_license
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/** @defgroup rcc_bdcr_values RCC_BDCR Values
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* @ingroup rcc_registers
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@{*/
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#define RCC_BDCR_BDRST (1 << 16)
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#define RCC_BDCR_RTCEN (1 << 15)
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#define RCC_BDCR_RTCSEL_MASK 0x3
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#define RCC_BDCR_RTCSEL_SHIFT 8
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#define RCC_BDCR_RTCSEL_NONE 0
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#define RCC_BDCR_RTCSEL_LSE 1
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#define RCC_BDCR_RTCSEL_LSI 2
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#define RCC_BDCR_RTCSEL_HSE 3
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#define RCC_BDCR_LSEDRV_MASK 0x3
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#define RCC_BDCR_LSEDRV_SHIFT 3
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#define RCC_BDCR_LSEDRV_LOW 0
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#define RCC_BDCR_LSEDRV_MEDH 1 /* good job st */
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#define RCC_BDCR_LSEDRV_MEDL 2
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#define RCC_BDCR_LSEDRV_HIGH 3
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#define RCC_BDCR_LSEBYP (1 << 2)
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#define RCC_BDCR_LSERDY (1 << 1)
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#define RCC_BDCR_LSEON (1 << 0)
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#define RCC_BDCR_BDRST (1U << 16U)
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#define RCC_BDCR_RTCEN (1U << 15U)
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#define RCC_BDCR_RTCSEL_MASK 0x3U
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#define RCC_BDCR_RTCSEL_SHIFT 8U
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#define RCC_BDCR_RTCSEL_NONE 0U
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#define RCC_BDCR_RTCSEL_LSE 1U
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#define RCC_BDCR_RTCSEL_LSI 2U
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#define RCC_BDCR_RTCSEL_HSE 3U
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#define RCC_BDCR_LSEDRV_MASK 0x3U
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#define RCC_BDCR_LSEDRV_SHIFT 3U
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#define RCC_BDCR_LSEDRV_LOW 0U
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#define RCC_BDCR_LSEDRV_MEDH 1U /* good job st */
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#define RCC_BDCR_LSEDRV_MEDL 2U
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#define RCC_BDCR_LSEDRV_HIGH 3U
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#define RCC_BDCR_LSEBYP (1U << 2U)
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#define RCC_BDCR_LSERDY (1U << 1U)
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#define RCC_BDCR_LSEON (1U << 0U)
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/**@}*/
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/** @defgroup rcc_csr_values RCC_CSR Values.
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* @ingroup rcc_registers
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@{*/
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#define RCC_CSR_LSIRDY (1 << 1)
|
||||
#define RCC_CSR_LSION (1 << 0)
|
||||
#define RCC_CSR_LSIRDY (1U << 1U)
|
||||
#define RCC_CSR_LSION (1U << 0U)
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup rcc_d1ccipr_values RCC_D1CCIP1R Values
|
||||
* @ingroup rcc_registers
|
||||
* @{*/
|
||||
#define RCC_D1CCIPR_CKPERSEL_HSI 0
|
||||
#define RCC_D1CCIPR_CKPERSEL_CSI 1
|
||||
#define RCC_D1CCIPR_CKPERSEL_HSE 2
|
||||
#define RCC_D1CCIPR_CKPERSEL_DISABLE 3
|
||||
#define RCC_D1CCIPR_CKPERSEL_HSI 0U
|
||||
#define RCC_D1CCIPR_CKPERSEL_CSI 1U
|
||||
#define RCC_D1CCIPR_CKPERSEL_HSE 2U
|
||||
#define RCC_D1CCIPR_CKPERSEL_DISABLE 3U
|
||||
/**@}*/
|
||||
#define RCC_D1CCIPR_CKPERSEL_SHIFT 28
|
||||
#define RCC_D1CCIPR_CKPERSEL_MASK 3
|
||||
#define RCC_D1CCIPR_CKPERSEL_SHIFT 28U
|
||||
#define RCC_D1CCIPR_CKPERSEL_MASK 3U
|
||||
|
||||
#define RCC_D2CCIP1R_SWPSEL_SHIFT 31
|
||||
#define RCC_D2CCIP1R_FDCANSEL_SHIFT 28
|
||||
#define RCC_D2CCIP1R_FDCANSEL_MASK 0x3
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT 24
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_SHIFT 20
|
||||
#define RCC_D2CCIP1R_SPI45SEL_SHIFT 16
|
||||
#define RCC_D2CCIP1R_SPI45SEL_MASK 0x7
|
||||
#define RCC_D2CCIP1R_SPI123SEL_SHIFT 12
|
||||
#define RCC_D2CCIP1R_SPI123SEL_MASK 0x7
|
||||
#define RCC_D2CCIP1R_SAI23SEL_SHIFT 6
|
||||
#define RCC_D2CCIP1R_SAISEL_MASK 0x7
|
||||
#define RCC_D2CCIP1R_SWPSEL_SHIFT 31U
|
||||
#define RCC_D2CCIP1R_FDCANSEL_SHIFT 28U
|
||||
#define RCC_D2CCIP1R_FDCANSEL_MASK 0x3U
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT 24U
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_SHIFT 20U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_SHIFT 16U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_MASK 0x7U
|
||||
#define RCC_D2CCIP1R_SPI123SEL_SHIFT 12U
|
||||
#define RCC_D2CCIP1R_SPI123SEL_MASK 0x7U
|
||||
#define RCC_D2CCIP1R_SAI23SEL_SHIFT 6U
|
||||
#define RCC_D2CCIP1R_SAISEL_MASK 0x7U
|
||||
|
||||
/** @defgroup rcc_d2ccip1r_values RCC_D2CCIP1R Values
|
||||
* @ingroup rcc_registers
|
||||
* @{*/
|
||||
#define RCC_D2CCIP1R_SWPSEL_PCLK 0x0
|
||||
#define RCC_D2CCIP1R_SWPSEL_HSI 0x1
|
||||
#define RCC_D2CCIP1R_FDCANSEL_HSE 0x0
|
||||
#define RCC_D2CCIP1R_FDCANSEL_PLL1Q 0x1
|
||||
#define RCC_D2CCIP1R_FDCANSEL_PLL2Q 0x2
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 0x0
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK 0x1
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_PLL1Q 0x0
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_PLL2R 0x1
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_PLL3R 0x2
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_HSI 0x3
|
||||
#define RCC_D2CCIP1R_SPI45SEL_APB4 0x0
|
||||
#define RCC_D2CCIP1R_SPI45SEL_PLL2Q 0x1
|
||||
#define RCC_D2CCIP1R_SPI45SEL_PLL3Q 0x2
|
||||
#define RCC_D2CCIP1R_SPI45SEL_HSI 0x3
|
||||
#define RCC_D2CCIP1R_SPI45SEL_CSI 0x4
|
||||
#define RCC_D2CCIP1R_SPI45SEL_HSE 0x5
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PLL1Q 0x0
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PLL2P 0x1
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PLL3P 0x2
|
||||
#define RCC_D2CCIP1R_SPI123SEL_I2SCKIN 0x3
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PERCK 0x4
|
||||
#define RCC_D2CCIP1R_SAISEL_PLL1Q 0x0
|
||||
#define RCC_D2CCIP1R_SAISEL_PLL2P 0x1
|
||||
#define RCC_D2CCIP1R_SAISEL_PLL3P 0x2
|
||||
#define RCC_D2CCIP1R_SAISEL_I2SCKIN 0x3
|
||||
#define RCC_D2CCIP1R_SAISEL_PERCK 0x4
|
||||
#define RCC_D2CCIP1R_SWPSEL_PCLK 0x0U
|
||||
#define RCC_D2CCIP1R_SWPSEL_HSI 0x1U
|
||||
#define RCC_D2CCIP1R_FDCANSEL_HSE 0x0U
|
||||
#define RCC_D2CCIP1R_FDCANSEL_PLL1Q 0x1U
|
||||
#define RCC_D2CCIP1R_FDCANSEL_PLL2Q 0x2U
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 0x0U
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK 0x1U
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_PLL1Q 0x0U
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_PLL2R 0x1U
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_PLL3R 0x2U
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_HSI 0x3U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_APB4 0x0U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_PLL2Q 0x1U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_PLL3Q 0x2U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_HSI 0x3U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_CSI 0x4U
|
||||
#define RCC_D2CCIP1R_SPI45SEL_HSE 0x5U
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PLL1Q 0x0U
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PLL2P 0x1U
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PLL3P 0x2U
|
||||
#define RCC_D2CCIP1R_SPI123SEL_I2SCKIN 0x3U
|
||||
#define RCC_D2CCIP1R_SPI123SEL_PERCK 0x4U
|
||||
#define RCC_D2CCIP1R_SAISEL_PLL1Q 0x0U
|
||||
#define RCC_D2CCIP1R_SAISEL_PLL2P 0x1U
|
||||
#define RCC_D2CCIP1R_SAISEL_PLL3P 0x2U
|
||||
#define RCC_D2CCIP1R_SAISEL_I2SCKIN 0x3U
|
||||
#define RCC_D2CCIP1R_SAISEL_PERCK 0x4U
|
||||
/**@}*/
|
||||
|
||||
#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT 28U
|
||||
@@ -421,18 +421,18 @@ LGPL License Terms @ref lgpl_license
|
||||
/** @defgroup rcc_d2ccip2r_values RCC_D2CCIP2R Values
|
||||
* @ingroup rcc_registers
|
||||
* @{*/
|
||||
#define RCC_D2CCIP2R_RNGSEL_HSI48 0
|
||||
#define RCC_D2CCIP2R_RNGSEL_PLL1Q 1
|
||||
#define RCC_D2CCIP2R_RNGSEL_LSE 2
|
||||
#define RCC_D2CCIP2R_RNGSEL_LSI 3
|
||||
#define RCC_D2CCIP2R_USART16SEL_PCLK2 0
|
||||
#define RCC_D2CCIP2R_USART234578SEL_PCLK1 0
|
||||
#define RCC_D2CCIP2R_USARTSEL_PCLK 0
|
||||
#define RCC_D2CCIP2R_USARTSEL_PLL2Q 1
|
||||
#define RCC_D2CCIP2R_USARTSEL_PLL3Q 2
|
||||
#define RCC_D2CCIP2R_USARTSEL_HSI 3
|
||||
#define RCC_D2CCIP2R_USARTSEL_CSI 4
|
||||
#define RCC_D2CCIP2R_USARTSEL_LSE 5
|
||||
#define RCC_D2CCIP2R_RNGSEL_HSI48 0U
|
||||
#define RCC_D2CCIP2R_RNGSEL_PLL1Q 1U
|
||||
#define RCC_D2CCIP2R_RNGSEL_LSE 2U
|
||||
#define RCC_D2CCIP2R_RNGSEL_LSI 3U
|
||||
#define RCC_D2CCIP2R_USART16SEL_PCLK2 0U
|
||||
#define RCC_D2CCIP2R_USART234578SEL_PCLK1 0U
|
||||
#define RCC_D2CCIP2R_USARTSEL_PCLK 0U
|
||||
#define RCC_D2CCIP2R_USARTSEL_PLL2Q 1U
|
||||
#define RCC_D2CCIP2R_USARTSEL_PLL3Q 2U
|
||||
#define RCC_D2CCIP2R_USARTSEL_HSI 3U
|
||||
#define RCC_D2CCIP2R_USARTSEL_CSI 4U
|
||||
#define RCC_D2CCIP2R_USARTSEL_LSE 5U
|
||||
/**@}*/
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user