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stm32/h7: Fixed an accuracy issue in the PLL clock input frequency calculation that resulted in all the follow-on calculations being way off in value

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dragonmux
2024-04-26 10:51:29 +01:00
committed by Piotr Esden-Tempski
parent 80ffd05933
commit 74ffe55dc5
1 changed files with 3 additions and 2 deletions
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5
lib/stm32/h7/rcc.c
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@@ -65,7 +65,8 @@ static void rcc_configure_pll(uint32_t clkin, const struct pll_config *config, i
uint8_t vco_addshift = 4 * (pll_num - 1); /* Values spaced by 4 for PLL 1/2/3 */ uint8_t vco_addshift = 4 * (pll_num - 1); /* Values spaced by 4 for PLL 1/2/3 */
/* Set the PLL input frequency range. */ /* Set the PLL input frequency range. */
uint32_t pll_clk_mhz = (clkin / config->divm) / HZ_PER_MHZ; uint32_t pll_clk = clkin / config->divm;
uint32_t pll_clk_mhz = pll_clk / HZ_PER_MHZ;
if (pll_clk_mhz > 2 && pll_clk_mhz <= 4) { if (pll_clk_mhz > 2 && pll_clk_mhz <= 4) {
RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_2_4MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_2_4MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift;
} else if (pll_clk_mhz > 4 && pll_clk_mhz <= 8) { } else if (pll_clk_mhz > 4 && pll_clk_mhz <= 8) {
@@ -75,7 +76,7 @@ static void rcc_configure_pll(uint32_t clkin, const struct pll_config *config, i
} }
/* Set the VCO output frequency range. */ /* Set the VCO output frequency range. */
uint32_t pll_vco_clk_mhz = (pll_clk_mhz * config->divn); uint32_t pll_vco_clk_mhz = (pll_clk * config->divn) / HZ_PER_MHZ;
if (pll_vco_clk_mhz <= 420) { if (pll_vco_clk_mhz <= 420) {
RCC_PLLCFGR |= (RCC_PLLCFGR_PLL1VCO_MED << vco_addshift); RCC_PLLCFGR |= (RCC_PLLCFGR_PLL1VCO_MED << vco_addshift);
} }