From 74ffe55dc50e94668a64ba1c2567048085670ab5 Mon Sep 17 00:00:00 2001 From: dragonmux Date: Fri, 26 Apr 2024 10:51:29 +0100 Subject: [PATCH] stm32/h7: Fixed an accuracy issue in the PLL clock input frequency calculation that resulted in all the follow-on calculations being way off in value --- lib/stm32/h7/rcc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/stm32/h7/rcc.c b/lib/stm32/h7/rcc.c index 163d14a5..02c8e23e 100644 --- a/lib/stm32/h7/rcc.c +++ b/lib/stm32/h7/rcc.c @@ -65,7 +65,8 @@ static void rcc_configure_pll(uint32_t clkin, const struct pll_config *config, i uint8_t vco_addshift = 4 * (pll_num - 1); /* Values spaced by 4 for PLL 1/2/3 */ /* Set the PLL input frequency range. */ - uint32_t pll_clk_mhz = (clkin / config->divm) / HZ_PER_MHZ; + uint32_t pll_clk = clkin / config->divm; + uint32_t pll_clk_mhz = pll_clk / HZ_PER_MHZ; if (pll_clk_mhz > 2 && pll_clk_mhz <= 4) { RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_2_4MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; } else if (pll_clk_mhz > 4 && pll_clk_mhz <= 8) { @@ -75,7 +76,7 @@ static void rcc_configure_pll(uint32_t clkin, const struct pll_config *config, i } /* Set the VCO output frequency range. */ - uint32_t pll_vco_clk_mhz = (pll_clk_mhz * config->divn); + uint32_t pll_vco_clk_mhz = (pll_clk * config->divn) / HZ_PER_MHZ; if (pll_vco_clk_mhz <= 420) { RCC_PLLCFGR |= (RCC_PLLCFGR_PLL1VCO_MED << vco_addshift); }