Adds handling for missing cases. While i2c only has 3 cases, uarts have
all 4, so make sure they're handled properly.
Removes duplicated/redundant definitions.
Adds doxygen wrappers, even if only for internal use.
Fixes: e41ac6ea71 stm32: added peripheral clock get helpers for all stm32
Signed-of-by: Karl Palsson <karlp@tweak.au>
It's simply a wrapper around rcc_reset_pulse already.
Just drop it. See 034dbf20ff for the same deletion for timers.
Signed-off-by: Karl Palsson <karlp@tweak.au>
It's simply a wrapper around rcc_reset_pulse already.
Just drop it. See 034dbf20ff for the same deletion for timers.
Signed-off-by: Karl Palsson <karlp@tweak.au>
A bunch of periphs on newer parts weren't defined. Add their
enable/reset bit definitions so they can be used.
Signed-off-by: Karl Palsson <karlp@tweak.au>
Updated to RM0444_rev5
Breaking: renames some irqs to be more specific and better match with
refman. We're still in the "between" tags, so break all the toys!
Signed-off-by: Karl Palsson <karlp@tweak.au>
Avoid use of the gnu specific "asm" keyword, and use the __asm__
keyword, as used everywhere else in the library. This fixes compilation
in C11, and unifies all uses of asm literals in the codebase.
Reported-by: @dragonmux
Fixes: https://github.com/libopencm3/libopencm3/pull/1425
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
- rcc_get_i2c_clk_freq: Add support by taking RCC_CCIPR2 into account for I2C4.
- rcc_get_timer_clk_freq: Add support for LP timers
- rcc_get_usart_clk_freq: Fix APB freq used for LPUART1 and UART1, respectively.
This commit adds support for NRF52 TWI Master mode and slightly extends
existing I2C API. This is a breaking change, while mode selection needs to be
done during enabling I2C. There is one additional breaking change done because:
1) Unicore MX API design was PITA for writes
2) It is incompatible with EasyDMA
I strongly apologize to all two users who might be affected by this change.
* added: Linker script adds support for RAM4 and RAM5 memory regions, so
that those are usable by code. This also fixes the fact that RAM4 was
declared, but inaccessible previously
* changed: RAM1 is renamed to RAM2, shifting numbering of all regions.
This is done in order to be in line with other STM32 definitions,
similarly ROM1 became ROM2.
by making it vaguer. These days, there's extra timers that support the
BDTR register, so the simple "advanced" timer description is no longer
sufficiently clear. You have to check your particular reference manual.
Fixes: https://github.com/libopencm3/libopencm3/issues/1378
