67c979e5fa
Fixed compile of f4 and l1 after gpio_common_f234.c renaming.
2013-07-07 16:01:46 -07:00
be874f065a
Memory map for f3 added.
2013-07-07 16:01:46 -07:00
a156b9e8fc
linker script file for f3 added.
2013-07-07 16:01:45 -07:00
3af5833b83
Initial support for stm32f3. Changes in makefiles, gpio.
...
- Makefiles now include building f3 src directory.
- Gpio support added. gpio_common_f24 changed to support also f3.
- f3 still not compiling, but f2 compile not broken (probably also f4).
2013-07-07 16:01:45 -07:00
d7fdcefbd7
lpc43xx: Fix rom_to_ram linker script
...
It was missing some definitions compared to the libopencm3_lpc43xx.ld.
2013-07-07 18:22:56 -04:00
8769073266
[install] Be more specific about what scripts we want to install.
...
We now have a subdirectory containing register definitions in scripts,
this confuses the install command so we have to be more specific about
which scripts to install. We actually only want to install the black
magic scripts from there as they are useful for locm3 users.
2013-07-07 14:11:58 -07:00
b72a3640b3
[CM0] Disabled sync for LPC43xx/M0.
...
We are currently using the same code for CM0 CM3 and CM4 cores. This
patch is a bodge that disables sync on the LPC43xx/M0 core, it would be
nicer to probably implement a dispatch system similar to the one used in
stm32 peripheral support so that we can accomodate the different
features of the cortex cores. I (esden) assume we will run into more
incompatibilities in the future between the cortex cores.
2013-07-07 13:58:00 -07:00
cd1f6fac80
sync.h: Fix spelling
2013-07-07 13:52:16 -07:00
11ea9b090c
sync: Add comment
2013-07-07 13:52:16 -07:00
78081bd794
lpc43xx: Add irq.yaml for M0 core
2013-07-07 13:52:16 -07:00
c25461dfce
lpc43xx: Move M4 specific files to m4/
2013-07-07 13:52:15 -07:00
3ab761d244
Remove dead lpc43xx_m0/vector.c
2013-07-07 13:52:15 -07:00
9aa2f82164
lpc32xx_ram_only.ld: Fix region name
2013-07-07 13:52:15 -07:00
8eb5fba93b
lpc43xx/uart: Fix code style
2013-07-07 13:52:15 -07:00
fa47bb80d5
lpc43xx/uart: Fix TER register definition
...
I'm not sure why bit 7 and offset 0x30 were used previously. Revision
1.6 of UM10503 claims that the TXEN bit is bit 0 in all UARTs' TER
registers.
2013-07-07 13:52:15 -07:00
dbf9c3bc39
lpc43xx/uart: Kill _BITMASK definitions for single-bit fields
2013-07-07 13:52:15 -07:00
b0550ce0bf
lpc43xx/uart: Uncomment register definitions
2013-07-07 13:52:15 -07:00
2b027cf2de
Makefile: Install everything in scripts/
2013-07-07 13:52:14 -07:00
8201703e64
lpc43xx/ssp: Fix duplicate function definition from merge
2013-07-07 13:52:14 -07:00
994e679fb8
lpc43xx: Clean up linker script breakage from merge
2013-07-07 13:52:14 -07:00
580be39e47
lpc43xx: Convert register definitions to YAML
2013-07-07 13:52:14 -07:00
4fd218ad4c
lpc43xx/gen.py: Take YAML input
2013-07-07 13:52:14 -07:00
4d6a5d9606
lpc43xx: Move YAML OrderedDict code to separate module
2013-07-07 13:52:14 -07:00
21e4d4600f
lpc43xx: Add script to convert CSV files to YAML
2013-07-07 13:52:14 -07:00
036cb51676
lpc43xx/gpdma.csv: Fix INTSTAT register name
2013-07-07 13:52:14 -07:00
e8af7a98ee
lpc43xx/ssp: Add ssp_transfer
2013-07-07 13:52:13 -07:00
0d29b1d2d6
lpc43: Use uint*_t instead of u*
2013-07-07 13:52:13 -07:00
26162762b7
lpc43xx: Update linker scripts
2013-07-07 13:52:13 -07:00
fa9fa986df
lpc43xx/uart: Add missing BEGIN/END_DECLS
2013-07-07 13:52:13 -07:00
17fd708f66
Move lpc43xx and lpc43xx_m0 code to lpc43xx/ hierarchy
...
Previously there were nasty dependency issues causing M4 objects to be
linked into the M0 library
2013-07-07 13:52:13 -07:00
16424d1c69
m0: remove useless remap
...
The m4 will 1) remap 2) start the m0, so it already is remapped, if it's
not, then we'd never execute this code anyway.
2013-07-07 13:52:13 -07:00
4c8d260232
make sure the m0 is really running/stopped
2013-07-07 13:52:13 -07:00
e5a4dd0609
Cleanup M0 makefile to avoid copying file from lpc43xx(M4) directory.
2013-07-07 13:52:13 -07:00
786e3215a4
Fixed a problem with rom to ram. (which can produce error "cannot move location counter backwards")
2013-07-07 13:52:12 -07:00
0dec187fee
lpc43xx basic IPC for multicore M4 & M0 (with basic examples for hackrf jellybean).
2013-07-07 13:52:12 -07:00
439957155b
Added SGPIO structure for faster/better code generation (especially when optimized with -O2/-O3).
...
This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3 September 2012.
2013-07-07 13:52:12 -07:00
edab264704
Added _data_rom / _edata_rom for ld ram only and standard spifi ld Fixed ROM to RAM copy of ".data"
2013-07-07 13:52:12 -07:00
f4e45e74bc
Add a duty cycle count argument to i2c0_init() to adjust for changes in APB1 clock.
2013-07-07 13:52:12 -07:00
18bcbc3d28
Consolidate ssp_read and ssp_write into a single function, ssp_transfer. SSP bus transfers are bi-directional -- when bytes are written, they are also read.
2013-07-07 13:52:12 -07:00
25d7853422
Switch ssp.c to using CGU #defines instead of local #defines.
2013-07-07 13:52:12 -07:00
0f180ceffd
do not try to install scripts/data
2013-07-07 13:52:12 -07:00
df922b9021
Corrected GPDMA_INTSTAT #define name typo.
2013-07-07 13:52:11 -07:00
b44631f3b1
Removed #defines for GPDMA channel base addresses, changed "API" on other #defines to accept an ordinal instead.
2013-07-07 13:52:11 -07:00
78884cef16
Changed GPDMA_CHANNELx #defines to use correct ("GPDMA_BASE") value as peripheral base address.
2013-07-07 13:52:11 -07:00
0dc4443e26
Renamed DMA_BASE to GPDMA_BASE to match peripheral name (and #defines in gpdma.h).
2013-07-07 13:52:11 -07:00
518b97efb6
Added generated headers and hand-crafted #defines for register fields common across many register sets.
2013-07-07 13:52:11 -07:00
8abefef07d
Rename indexed #define macros for channel-specific GPDMA registers, to match documentation and avoid conflict with the GPDMA_CONFIG register name.
2013-07-07 13:52:10 -07:00
e9eacc60ac
Change header generation script to produce function-like #define macros for single-bit fields, too.
2013-07-07 13:52:10 -07:00
b1e5c77e1d
New SGPIO field #defines, generated from sgpio.csv.
2013-07-07 13:52:10 -07:00
5359dd245e
Fixed typo in SGPIO_MUX_CFGx CLK_SOURCE_SLICE_MODE bit offset and width.
2013-07-07 13:52:10 -07:00
Federico Ruiz Ugalde