07868ad8b6
stm32f7: enable existing dma2d headers
2019-05-19 21:33:07 +00:00
82498bb49f
stm32f7: fixed typos in dsi header definitions
2019-05-19 21:33:07 +00:00
92a2340551
stm32f7: enable existing dsi support
2019-05-19 21:33:07 +00:00
5a03cfe54e
stm32f7: enable existing ltdc
...
This uses the existing f4 code as a new shared common base code.
2019-05-19 21:33:02 +00:00
16cfc6d848
stm32f7: enable fsmc
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This uses the existing f4 code as a new shared common base code.
2019-05-19 21:30:48 +00:00
4fc7196463
stm32f7: enable existing exti headers
2019-05-19 21:30:38 +00:00
c801a7ffec
stm32f7: Rename USART7/8 to UART7/8.
...
Matches the existing irq names and the reference manual correctly.
2019-05-19 20:43:57 +00:00
888fee1409
stm32l1: adc: use the new v1-multi headers.
...
This drops a lot of now common definitions. This is still just
prepratory work before using the v1-multi code itself.
2019-05-10 22:35:10 +00:00
c858a1e5f5
stm32: adc-v1m: extract some portions back to f4/f7.
...
While this appears to be a backward change, this moves the _register_
definitions (their addresses) and the actually specific to f4/f7
numbering back into the explicit headers. Potentially this could be
pulled out again, but it's not much code.
This then allows the stm32l1 to use all the rest of this code, with the
differences really being just the addresses of the registers.
2019-05-10 22:30:31 +00:00
7076619dd7
stm32: adc-v1m: drop lots of noisy useless defines.
...
Never seen any reason for these noisy verbose defines. They're not
helpful, and we've never needed them for doing sequence setting code
anyway. Just drop them.
2019-05-10 22:27:20 +00:00
53c6e617b5
stm32: adc-v1m: tightenup definitions
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Use the masks and shifts defined. common style.
2019-05-10 22:20:29 +00:00
45e14a7bd3
stm32: adc: fix f4/f7 temperature sensor channel defines.
...
Lots of common stuff, but the F7 fixed the temperature sensor randomness
that the f4 had. Separate the definitions properly.
2019-05-10 22:18:08 +00:00
cc364d1ac2
stm32: adc-v1m: fix include guard
2019-05-10 22:16:33 +00:00
0a3e1cc0e6
Renamed adc_common_v3 to adc_common_v1_multi
2019-05-09 11:54:19 +00:00
6703abf5e3
Added F7 ADC support (almost the same as F4)
2019-05-09 11:54:19 +00:00
ca43a73ea3
stm32: dac: move DAC_SR to common.
...
It's available on f0, f2, f3, f4, f7, l0, l1 and l4.
Just note that it's not available on f1.
2019-05-09 11:49:25 +00:00
486446e1db
STM32F4-7: add DAC_SR status bits
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Include the DAC_SR register and it's bits. Arguably this should be jsut
included in the common_all file.
2019-05-09 11:39:44 +00:00
5dbdb255d8
STM32F7: dac: include in build.
...
Based on F4.
2019-05-09 11:34:16 +00:00
e50ce6a876
stm32l4: Correct memorymap and add the existing CAN library
2019-04-30 20:47:14 +02:00
4fb67d891f
stm32f7: enable existing ethernet libraries
2019-04-15 13:11:05 +00:00
395c024458
stm32f7: enable existing syscfg headers
2019-04-15 13:10:48 +00:00
a92a44a7c2
stm32f7: enable existing CRC support
2019-04-15 13:10:37 +00:00
0173ecec9c
stm32f7: enable existing IWDG support
2019-04-15 13:10:21 +00:00
72a7284355
doc: hook up gd32f1x0 documentation
...
Super easy now thanks to the earlier changes.
2019-04-15 13:06:48 +00:00
4db40e0839
stm32f7: Include i2c_common_v2
...
With the addition of a define for I2C4, the existing common i2c
functions seem to work out of the box on the F7 (tested on an
STM32F750).
2019-04-04 22:11:20 +00:00
330d5fd5be
gd32: add new chip series f1x0
...
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by
GigaDevice, which features pin-to-pin package compatibility with
STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds
CAN support.
Currently the code mainly targets GD32F130 and F150 chips. Some register
are different between F130/150 and F170/190, just like the difference
between STM32F1 Performance line and Connectivity line.
From the perspective of registers and memory map, GD32F1X0 seems like a
mixture between STM32F1 and STM32F0 (because it is designed to be
pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of
code are shared between STM32 and GD32, and these code are specially
processed to include the GD32 headers instead of STM32 headers when meet
GD32F1X0.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io >
Reviewed-by: Karl Palsson <karlp@tweak.net.au >
gd32/rcc.[ch] are forks of stm32f1/rcc
gd32/flash.[ch] are forks of stm32f0/flash
No attempts at deduplicating this have been done at this stage. We can
see where they move in the future.
2019-04-03 12:53:33 +00:00
8064f6d0cb
stm32f4: fmc: add missing DECLS wrappers
...
Function prototypes need DECLS wrappers for inclusion in c++/asm
2019-01-31 09:59:59 +00:00
553c876fa5
stm32: exti: define AFIO/SYSCFG_EXTICR_FIELDSIZE for all chip.
...
While on all current chips, exticr gpio port mux selection is coded on 4 bits,
stm32g0 EXTI_EXTICR register uses 8 bits. Align all exti header to reference
that value (was previously defined for f0 as SYCFG_EXTICR_SKIP)
2019-01-31 09:57:43 +00:00
7afd86db30
stm32l[01]: flash common: add flash_unlock_acr, allowing to unlock FLASH_ACR RUN_PD bit.
...
flash_unlock_acr allows to unlock RUN_PD bit from FLASH_ACR register. Relock is done automatically
when writing 0 to RUN_PD, so no flash_lock_acr method.
2019-01-31 09:35:55 +00:00
ff9664389b
stm32: exti: move register definition of all current stm32 devices to common_v1
...
Preparation for stm32g0 support, as this chip's exti register map evolved and is
no longer common ...
2019-01-18 18:33:55 +01:00
9cadd60b3c
stm32: rtc: Fixed typo in macro def (RTC_DR_MT_MASK)
2019-01-18 10:32:43 +00:00
708fe1516c
stm32: fix nvic channels name to match dma1/2 on stm32f09x
2019-01-18 10:31:32 +00:00
718f86935a
EFM32 I2C: fix base undeclared
...
libopencm3/include/libopencm3/efm32/common/i2c_common.h:234:29: error: 'base' undeclared (first use in this function)
#define I2C0_CTRL I2C_CTRL(base)
2019-01-14 11:51:08 +00:00
33387e8f96
stm32f0:adc: add missing declaration
...
fixes: 7e1d3daa
2019-01-12 22:19:49 +00:00
4edba3111d
common: support inclusion into assembly files
...
Suggested in https://github.com/libopencm3/libopencm3/pull/981
2019-01-11 23:09:27 +00:00
ad10e96811
stm32l4:dma: add Channel Selection defines
...
Far from complete support for the channel selection systems on f0/l4,
but at least brings in the defines needed for doing this yourself.
Fixes https://github.com/libopencm3/libopencm3/issues/1001
2018-12-30 21:03:40 +00:00
1adc418f9a
stm32f42/f43: rcc: add 180 MHz clock options
2018-11-12 21:41:05 +00:00
8b13977ea0
stm32f0: add DMA1 compatibility alias
2018-11-09 15:34:58 +00:00
b7a9968e4f
fixup! stm32f09: add register definitions for DMA2
2018-11-06 18:48:18 +01:00
a9c0008290
stm32f09: add register definitions for DMA2
2018-11-06 12:58:36 +01:00
53347c266b
stm32f09: add register definitions for USART5..8
2018-11-06 11:35:40 +01:00
3af05fb862
stm32f7: spi: fix include error
...
Badly splitting commits.
Fixes: 2619a45
2018-10-23 21:43:29 +00:00
1883a4311f
msp432: whitespace fixups spaces->tabs
...
whitespace only change.
2018-10-23 21:33:16 +00:00
a63d0499de
msp432/e4: Add GPIO support
2018-10-23 21:21:54 +00:00
076cd67530
stm32: spi-v2: Frame format is available for all.
...
All spi v2 peripherals include the Motorola/TI Frame formatting options
introduced with F2.
2018-10-23 21:21:36 +00:00
f6517f7816
stm32: adc common v2: add circular dma mode
...
Tested only on the F3 so far.
2018-10-20 11:46:47 +00:00
bc7e454741
stm32f7: include common dma code
...
Originally reported at https://github.com/libopencm3/libopencm3/pull/978
2018-10-20 11:40:38 +00:00
18eadcfda5
stm32: timer_common: add timer21-22, found on stm32l0 chips.
...
stm32l0 devices have tim21 and tim22.
2018-10-06 09:53:54 +00:00
239b4a4704
stm32f7: add irqs from latest ref manuals
...
Updated from RM410 rev4, RM0385rev8 and RM0431 rev3
Originally reported at https://github.com/libopencm3/libopencm3/issues/974
2018-10-03 17:12:42 +00:00
6b0fd864a1
stm32f7: fix RCC_APB1 defns for USART7/USART8
...
The reset and low power definitions for USART7/USART8 were correct, but
not the primary enable registers.
Fixes: https://github.com/libopencm3/libopencm3/issues/969
2018-09-24 10:35:16 +00:00
Oliver Meier