gd32: add new chip series f1x0
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by GigaDevice, which features pin-to-pin package compatibility with STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds CAN support. Currently the code mainly targets GD32F130 and F150 chips. Some register are different between F130/150 and F170/190, just like the difference between STM32F1 Performance line and Connectivity line. From the perspective of registers and memory map, GD32F1X0 seems like a mixture between STM32F1 and STM32F0 (because it is designed to be pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of code are shared between STM32 and GD32, and these code are specially processed to include the GD32 headers instead of STM32 headers when meet GD32F1X0. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Karl Palsson <karlp@tweak.net.au> gd32/rcc.[ch] are forks of stm32f1/rcc gd32/flash.[ch] are forks of stm32f0/flash No attempts at deduplicating this have been done at this stage. We can see where they move in the future.
This commit is contained in:
Icenowy Zheng
committed by
Karl Palsson
Karl Palsson
parent
d109a1ddeb
commit
330d5fd5be
@@ -21,6 +21,9 @@
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#elif defined(STM32L4)
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# include <libopencm3/stm32/l4/nvic.h>
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#elif defined(GD32F1X0)
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# include <libopencm3/gd32/f1x0/nvic.h>
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#elif defined(EFM32TG)
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# include <libopencm3/efm32/tg/nvic.h>
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#elif defined(EFM32G)
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103
include/libopencm3/gd32/f1x0/flash.h
Normal file
103
include/libopencm3/gd32/f1x0/flash.h
Normal file
@@ -0,0 +1,103 @@
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/** @defgroup flash_defines FLASH Defines
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*
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* @brief <b>Defined Constants and Types for the GD32F1x0 Flash memory</b>
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*
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* @ingroup GD32F1x0_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2013
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* Frantisek Burian <BuFran@seznam.cz>
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*
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* @date 14 January 2014
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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/**@{*/
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#include <libopencm3/stm32/common/flash_common_all.h>
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#include <libopencm3/stm32/common/flash_common_f.h>
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#include <libopencm3/stm32/common/flash_common_f01.h>
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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/* --- FLASH_ACR values ---------------------------------------------------- */
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/** @defgroup flash_latency FLASH Wait States
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@ingroup flash_defines
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@{*/
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#define FLASH_ACR_LATENCY_000_024MHZ 0
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#define FLASH_ACR_LATENCY_024_048MHZ 1
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#define FLASH_ACR_LATENCY_048_072MHZ 2
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#define FLASH_ACR_LATENCY_0WS 0
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#define FLASH_ACR_LATENCY_1WS 1
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#define FLASH_ACR_LATENCY_2WS 1
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/**@}*/
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/* --- FLASH_SR values ----------------------------------------------------- */
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#define FLASH_SR_EOP (1 << 5)
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#define FLASH_SR_WRPRTERR (1 << 4)
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#define FLASH_SR_PGERR (1 << 2)
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#define FLASH_SR_BSY (1 << 0)
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/* --- FLASH_CR values ----------------------------------------------------- */
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#define FLASH_CR_OBL_LAUNCH (1 << 13)
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/* --- FLASH_OBR values ---------------------------------------------------- */
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#define FLASH_OBR_DATA1_SHIFT 24
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#define FLASH_OBR_DATA1 (0xFF << FLASH_OBR_DATA1_SHIFT)
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#define FLASH_OBR_DATA0_SHIFT 16
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#define FLASH_OBR_DATA0 (0xFF << FLASH_OBR_DATA0_SHIFT)
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#define FLASH_OBR_USER_SHIFT 8
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#define FLASH_OBR_USER (0xFF << FLASH_OBR_USER_SHIFT)
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#define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT)
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#define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT)
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#define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT)
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#define FLASH_OBR_RDPRT_L2 (3 << FLASH_OBR_RDPRT_SHIFT)
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/*****************************************************************************/
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/* API definitions */
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/*****************************************************************************/
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/* Read protection option byte protection level setting */
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#define FLASH_RDP_L0 ((uint8_t)0xa5)
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#define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */
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#define FLASH_RDP_L2 ((uint8_t)0xcc)
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/*****************************************************************************/
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/* API Functions */
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/*****************************************************************************/
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BEGIN_DECLS
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END_DECLS
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/**@}*/
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#endif
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31
include/libopencm3/gd32/f1x0/gpio.h
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31
include/libopencm3/gd32/f1x0/gpio.h
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@@ -0,0 +1,31 @@
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/** @defgroup gpio_defines GPIO Defines
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*
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* @brief <b>Defined Constants and Types for the GD32F1x0 General Purpose I/O</b>
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*
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* @ingroup GD32F1x0_defines
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*
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* @version 1.0.0
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*
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* @date 1 July 2012
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f0/gpio.h>
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59
include/libopencm3/gd32/f1x0/irq.json
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59
include/libopencm3/gd32/f1x0/irq.json
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@@ -0,0 +1,59 @@
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{
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"irqs": [
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"wwdg",
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"pvd",
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"rtc",
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"flash",
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"rcc",
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"exti0_1",
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"exti2_3",
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"exti4_15",
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"tsc",
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"dma_channel1",
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"dma_channel2_3",
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"dma_channel4_5",
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"adc_comp",
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"tim1_brk_up_trg_com",
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"tim1_cc",
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"tim2",
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"tim3",
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"tim6_dac",
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"reserved0",
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"tim14",
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"tim15",
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"tim16",
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"tim17",
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"i2c1_ev",
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"i2c2_ev",
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"spi1",
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"spi2",
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"usart1",
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"usart2",
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"reserved1",
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"cec_can",
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"reserved2",
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"i2c1_er",
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"reserved3",
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"i2c2_er",
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"i2c3_ev",
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"i2c3_er",
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"usb_lp",
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"usb_hp",
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"reserved4",
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"reserved5",
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"reserved6",
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"usb_wakeup",
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"reserved7",
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"reserved8",
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"reserved9",
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"reserved10",
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"reserved11",
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"dma_channel6_7",
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"reserved12",
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"reserved13",
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"spi3"
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],
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"partname_humanreadable": "GD32F1x0 Series",
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"partname_doxygen": "GD32F1x0",
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"includeguard": "LIBOPENCM3_GD32F1X0_NVIC_H"
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}
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109
include/libopencm3/gd32/f1x0/memorymap.h
Normal file
109
include/libopencm3/gd32/f1x0/memorymap.h
Normal file
@@ -0,0 +1,109 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Iceonwy Zheng <icenowy@aosc.io>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- GD32 specific peripheral definitions ------------------------------- */
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/* Memory map for all buses */
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#define FLASH_BASE (0x08000000U)
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#define PERIPH_BASE (0x40000000U)
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#define INFO_BASE (0x1ffff000U)
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
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#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
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#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
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#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x8000000)
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/* Register boundary addresses */
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
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#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
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#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
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/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
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#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
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/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
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#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
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/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
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#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define BACKUP_REGS_BASE (RTC_BASE + 0x50)
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
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#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800)
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/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */
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/* APB2 */
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#define SYSCFG_COMP_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
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#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
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#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
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#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)
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#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)
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#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)
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/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */
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/* AHB1 */
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#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x00000)
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#define RCC_BASE (PERIPH_BASE_AHB1 + 0x01000)
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x02000)
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#define CRC_BASE (PERIPH_BASE_AHB1 + 0x03000)
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#define TSC_BASE (PERIPH_BASE_AHB1 + 0x03000)
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/* AHB 2 */
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#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)
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#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)
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#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)
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#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)
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#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
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#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7ac)
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/* Ignore the "reserved for future use" half of the first word */
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#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
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#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
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#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
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#endif
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526
include/libopencm3/gd32/f1x0/rcc.h
Normal file
526
include/libopencm3/gd32/f1x0/rcc.h
Normal file
@@ -0,0 +1,526 @@
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/** @defgroup rcc_defines RCC Defines
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*
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* @brief <b>Defined Constants and Types for the GD32F1x0 Reset and Clock
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* Control</b>
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*
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* @ingroup GD32F1x0_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2009
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* Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
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* @author @htmlonly © @endhtmlonly 2009
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* Uwe Hermann <uwe@hermann-uwe.de>
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*
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* @date 18 August 2012
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*
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* LGPL License Terms @ref lgpl_license
|
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* */
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/*
|
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* This file is part of the libopencm3 project.
|
||||
*
|
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* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
|
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
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/**@{*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
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#define RCC_CIR MMIO32(RCC_BASE + 0x08)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
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#define RCC_CSR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)
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#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c)
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#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30)
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#define RCC_CR2 MMIO32(RCC_BASE + 0x34)
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/* --- RCC_CR values ------------------------------------------------------- */
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_CSSON (1 << 19)
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#define RCC_CR_HSEBYP (1 << 18)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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/* HSICAL: [15:8] */
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/* HSITRIM: [7:3] */
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
|
||||
|
||||
/* --- RCC_CFGR values ----------------------------------------------------- */
|
||||
|
||||
#define RCC_CFGR_PLLNODIV (1 << 31)
|
||||
|
||||
#define RCC_CFGR_MCOPRE_SHIFT 28
|
||||
#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
|
||||
#define RCC_CFGR_PLLMUL_4_SHIFT 27
|
||||
#define RCC_CFGR_PLLMUL_4 (1 << RCC_CFGR_PLLMUL_4_SHIFT)
|
||||
|
||||
#define RCC_CFGR_MCO_SHIFT 24
|
||||
#define RCC_CFGR_MCO_MASK 0x7
|
||||
#define RCC_CFGR_MCO_NOCLK 0
|
||||
#define RCC_CFGR_MCO_HSI14 1
|
||||
#define RCC_CFGR_MCO_LSI 2
|
||||
#define RCC_CFGR_MCO_LSE 3
|
||||
#define RCC_CFGR_MCO_SYSCLK 4
|
||||
#define RCC_CFGR_MCO_HSI 5
|
||||
#define RCC_CFGR_MCO_HSE 6
|
||||
#define RCC_CFGR_MCO_PLL 7
|
||||
|
||||
#define RCC_CFGR_USBPRE_SHIFT 22
|
||||
#define RCC_CFGR_USBPRE (3 << RCC_CFGR_USBPRE_SHIFT)
|
||||
|
||||
#define RCC_CFGR_PLLMUL_0_3_SHIFT 18
|
||||
#define RCC_CFGR_PLLMUL_0_3 (0xF << RCC_CFGR_PLLMUL_0_3_SHIFT)
|
||||
|
||||
#define RCC_CFGR_PLLXTPRE (1 << 17)
|
||||
#define RCC_CFGR_PLLSRC (1 << 16)
|
||||
|
||||
#define RCC_CFGR_ADCPRE_SHIFT 14
|
||||
#define RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT)
|
||||
|
||||
#define RCC_CFGR_PPRE2_SHIFT 11
|
||||
#define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT)
|
||||
|
||||
#define RCC_CFGR_PPRE1_SHIFT 8
|
||||
#define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
|
||||
#define RCC_CFGR_HPRE_SHIFT 4
|
||||
#define RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT)
|
||||
|
||||
#define RCC_CFGR_SWS_SHIFT 2
|
||||
#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT)
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT 0
|
||||
#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT)
|
||||
|
||||
/* USBPRE: USB prescaler (RCC_CFGR[23:22]) */
|
||||
#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
|
||||
#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
|
||||
#define RCC_CFGR_USBPRE_PLL_CLK_DIV2_5 0x2
|
||||
#define RCC_CFGR_USBPRE_PLL_CLK_DIV2 0x3
|
||||
|
||||
/* PLLMUL: PLL multiplication factor */
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd
|
||||
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe
|
||||
|
||||
/* PLLXTPRE: HSE divider for PLL entry */
|
||||
#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
|
||||
#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
|
||||
|
||||
/* PLLSRC: PLL entry clock source */
|
||||
#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
|
||||
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
|
||||
|
||||
/* ADCPRE: ADC prescaler */
|
||||
/****************************************************************************/
|
||||
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
|
||||
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
|
||||
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
|
||||
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
|
||||
|
||||
/* PPRE2: APB high-speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
|
||||
|
||||
/* PPRE1: APB low-speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
|
||||
|
||||
/* HPRE: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
|
||||
|
||||
/* SWS: System clock switch status */
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
|
||||
|
||||
/* SW: System clock switch */
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
|
||||
|
||||
/* --- RCC_CIR values ------------------------------------------------------ */
|
||||
|
||||
/* Clock security system interrupt clear bit */
|
||||
#define RCC_CIR_CSSC (1 << 23)
|
||||
|
||||
/* OSC ready interrupt clear bits */
|
||||
#define RCC_CIR_HSI14RDYC (1 << 21)
|
||||
#define RCC_CIR_PLLRDYC (1 << 20)
|
||||
#define RCC_CIR_HSERDYC (1 << 19)
|
||||
#define RCC_CIR_HSIRDYC (1 << 18)
|
||||
#define RCC_CIR_LSERDYC (1 << 17)
|
||||
#define RCC_CIR_LSIRDYC (1 << 16)
|
||||
|
||||
/* OSC ready interrupt enable bits */
|
||||
#define RCC_CIR_HSI14RDYIE (1 << 13)
|
||||
#define RCC_CIR_PLLRDYIE (1 << 12)
|
||||
#define RCC_CIR_HSERDYIE (1 << 11)
|
||||
#define RCC_CIR_HSIRDYIE (1 << 10)
|
||||
#define RCC_CIR_LSERDYIE (1 << 9)
|
||||
#define RCC_CIR_LSIRDYIE (1 << 8)
|
||||
|
||||
/* Clock security system interrupt flag bit */
|
||||
#define RCC_CIR_CSSF (1 << 7)
|
||||
|
||||
/* OSC ready interrupt flag bits */
|
||||
#define RCC_CIR_HSI14RDYF (1 << 5)
|
||||
#define RCC_CIR_PLLRDYF (1 << 4)
|
||||
#define RCC_CIR_HSERDYF (1 << 3)
|
||||
#define RCC_CIR_HSIRDYF (1 << 2)
|
||||
#define RCC_CIR_LSERDYF (1 << 1)
|
||||
#define RCC_CIR_LSIRDYF (1 << 0)
|
||||
|
||||
/* --- RCC_APB2RSTR values ------------------------------------------------- */
|
||||
|
||||
#define RCC_APB2RSTR_TIM17RST (1 << 18)
|
||||
#define RCC_APB2RSTR_TIM16RST (1 << 17)
|
||||
#define RCC_APB2RSTR_TIM15RST (1 << 16)
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14)
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12)
|
||||
#define RCC_APB2RSTR_TIM1RST (1 << 11)
|
||||
#define RCC_APB2RSTR_ADCRST (1 << 9)
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
|
||||
|
||||
/* --- RCC_APB1RSTR values ------------------------------------------------- */
|
||||
|
||||
#define RCC_APB1RSTR_CECRST (1 << 30)
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29)
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28)
|
||||
#define RCC_APB1RSTR_USBRST (1 << 23)
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22)
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21)
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17)
|
||||
#define RCC_APB1RSTR_SPI3RST (1 << 15)
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14)
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11)
|
||||
#define RCC_APB1RSTR_TIM14RST (1 << 8)
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4)
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1)
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0)
|
||||
|
||||
/* --- RCC_AHBENR values --------------------------------------------------- */
|
||||
|
||||
#define RCC_AHBENR_TSCEN (1 << 24)
|
||||
#define RCC_AHBENR_GPIOFEN (1 << 22)
|
||||
#define RCC_AHBENR_GPIOEEN (1 << 21)
|
||||
#define RCC_AHBENR_GPIODEN (1 << 20)
|
||||
#define RCC_AHBENR_GPIOCEN (1 << 19)
|
||||
#define RCC_AHBENR_GPIOBEN (1 << 18)
|
||||
#define RCC_AHBENR_GPIOAEN (1 << 17)
|
||||
#define RCC_AHBENR_CRCEN (1 << 6)
|
||||
#define RCC_AHBENR_FLTFEN (1 << 4)
|
||||
#define RCC_AHBENR_SRAMEN (1 << 2)
|
||||
#define RCC_AHBENR_DMAEN (1 << 0)
|
||||
|
||||
/* --- RCC_APB2ENR values -------------------------------------------------- */
|
||||
|
||||
#define RCC_APB2ENR_TIM17EN (1 << 18)
|
||||
#define RCC_APB2ENR_TIM16EN (1 << 17)
|
||||
#define RCC_APB2ENR_TIM15EN (1 << 16)
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14)
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12)
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 11)
|
||||
#define RCC_APB2ENR_ADCEN (1 << 9)
|
||||
#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0)
|
||||
|
||||
/* --- RCC_APB1ENR values -------------------------------------------------- */
|
||||
|
||||
#define RCC_APB1ENR_CECEN (1 << 30)
|
||||
#define RCC_APB1ENR_DACEN (1 << 29)
|
||||
#define RCC_APB1ENR_PWREN (1 << 28)
|
||||
#define RCC_APB1ENR_USBEN (1 << 23)
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22)
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21)
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17)
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15)
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14)
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11)
|
||||
#define RCC_APB1ENR_TIM14EN (1 << 8)
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4)
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1)
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0)
|
||||
|
||||
/* --- RCC_BDCR values ----------------------------------------------------- */
|
||||
|
||||
#define RCC_BDCR_BDRST (1 << 16)
|
||||
#define RCC_BDCR_RTCEN (1 << 15)
|
||||
/* RCC_BDCR[9:8]: RTCSEL */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2)
|
||||
#define RCC_BDCR_LSERDY (1 << 1)
|
||||
#define RCC_BDCR_LSEON (1 << 0)
|
||||
|
||||
/* --- RCC_CSR values ------------------------------------------------------ */
|
||||
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31)
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30)
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29)
|
||||
#define RCC_CSR_SFTRSTF (1 << 28)
|
||||
#define RCC_CSR_PORRSTF (1 << 27)
|
||||
#define RCC_CSR_PINRSTF (1 << 26)
|
||||
#define RCC_CSR_RMVF (1 << 24)
|
||||
#define RCC_CSR_LSIRDY (1 << 1)
|
||||
#define RCC_CSR_LSION (1 << 0)
|
||||
|
||||
/* --- RCC_AHBRSTR values -------------------------------------------------- */
|
||||
|
||||
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
|
||||
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
|
||||
|
||||
/* --- RCC_CFGR2 values ---------------------------------------------------- */
|
||||
|
||||
#define RCC_CFGR2_PREDIV 0xf
|
||||
#define RCC_CFGR2_PREDIV_NODIV 0x0
|
||||
#define RCC_CFGR2_PREDIV_DIV2 0x1
|
||||
#define RCC_CFGR2_PREDIV_DIV3 0x2
|
||||
#define RCC_CFGR2_PREDIV_DIV4 0x3
|
||||
#define RCC_CFGR2_PREDIV_DIV5 0x4
|
||||
#define RCC_CFGR2_PREDIV_DIV6 0x5
|
||||
#define RCC_CFGR2_PREDIV_DIV7 0x6
|
||||
#define RCC_CFGR2_PREDIV_DIV8 0x7
|
||||
#define RCC_CFGR2_PREDIV_DIV9 0x8
|
||||
#define RCC_CFGR2_PREDIV_DIV10 0x9
|
||||
#define RCC_CFGR2_PREDIV_DIV11 0xa
|
||||
#define RCC_CFGR2_PREDIV_DIV12 0xb
|
||||
#define RCC_CFGR2_PREDIV_DIV13 0xc
|
||||
#define RCC_CFGR2_PREDIV_DIV14 0xd
|
||||
#define RCC_CFGR2_PREDIV_DIV15 0xe
|
||||
#define RCC_CFGR2_PREDIV_DIV16 0xf
|
||||
|
||||
/* --- RCC_CFGR3 values ---------------------------------------------------- */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_SHIFT 16
|
||||
#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT)
|
||||
#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT)
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)
|
||||
#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT)
|
||||
#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT)
|
||||
|
||||
#define RCC_CFGR3_ADCSW (1 << 8)
|
||||
#define RCC_CFGR3_CECSW (1 << 6)
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
extern uint32_t rcc_ahb_frequency;
|
||||
extern uint32_t rcc_apb1_frequency;
|
||||
extern uint32_t rcc_apb2_frequency;
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
enum rcc_clock_hsi {
|
||||
RCC_CLOCK_HSI_48MHZ,
|
||||
RCC_CLOCK_HSI_64MHZ,
|
||||
RCC_CLOCK_HSI_END
|
||||
};
|
||||
|
||||
enum rcc_clock_hse8 {
|
||||
RCC_CLOCK_HSE8_72MHZ,
|
||||
RCC_CLOCK_HSE8_END
|
||||
};
|
||||
|
||||
struct rcc_clock_scale {
|
||||
uint8_t pllmul;
|
||||
uint8_t hpre;
|
||||
uint8_t ppre1;
|
||||
uint8_t ppre2;
|
||||
uint8_t adcpre;
|
||||
uint8_t usbpre; /* Only valid if HSE used */
|
||||
bool use_hse; /* PLL source is HSE if set, HSI/2 if unset */
|
||||
uint8_t pll_hse_prediv; /* Only valid if HSE used */
|
||||
uint32_t ahb_frequency;
|
||||
uint32_t apb1_frequency;
|
||||
uint32_t apb2_frequency;
|
||||
};
|
||||
|
||||
extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_HSI_END];
|
||||
extern const struct rcc_clock_scale rcc_hse8_configs[RCC_CLOCK_HSE8_END];
|
||||
|
||||
enum rcc_osc {
|
||||
RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI
|
||||
};
|
||||
|
||||
#define _REG_BIT(base, bit) (((base) << 5) + (bit))
|
||||
|
||||
/* V = value line F100
|
||||
* N = standard line F101, F102, F103
|
||||
* C = communication line F105, F107
|
||||
*/
|
||||
enum rcc_periph_clken {
|
||||
|
||||
/* AHB peripherals */
|
||||
RCC_DMA = _REG_BIT(0x14, 0),
|
||||
RCC_SRAM = _REG_BIT(0x14, 2),
|
||||
RCC_FLTF = _REG_BIT(0x14, 4),
|
||||
RCC_CRC = _REG_BIT(0x14, 6),
|
||||
RCC_GPIOA = _REG_BIT(0x14, 17),
|
||||
RCC_GPIOB = _REG_BIT(0x14, 18),
|
||||
RCC_GPIOC = _REG_BIT(0x14, 19),
|
||||
RCC_GPIOD = _REG_BIT(0x14, 20),
|
||||
RCC_GPIOF = _REG_BIT(0x14, 22),
|
||||
RCC_TSC = _REG_BIT(0x14, 24),
|
||||
|
||||
/* APB2 peripherals */
|
||||
RCC_SYSCFG_COMP = _REG_BIT(0x18, 0),
|
||||
RCC_ADC = _REG_BIT(0x18, 9),
|
||||
RCC_TIM1 = _REG_BIT(0x18, 11),
|
||||
RCC_SPI1 = _REG_BIT(0x18, 12),
|
||||
RCC_USART1 = _REG_BIT(0x18, 14),
|
||||
RCC_TIM15 = _REG_BIT(0x18, 16),
|
||||
RCC_TIM16 = _REG_BIT(0x18, 17),
|
||||
RCC_TIM17 = _REG_BIT(0x18, 18),
|
||||
|
||||
/* APB1 peripherals */
|
||||
RCC_TIM2 = _REG_BIT(0x1C, 0),
|
||||
RCC_TIM3 = _REG_BIT(0x1C, 1),
|
||||
RCC_TIM6 = _REG_BIT(0x1C, 4),
|
||||
RCC_TIM14 = _REG_BIT(0x1C, 8),
|
||||
RCC_WWDG = _REG_BIT(0x1C, 11),
|
||||
RCC_SPI2 = _REG_BIT(0x1C, 14),
|
||||
RCC_SPI3 = _REG_BIT(0x1C, 15),
|
||||
RCC_USART2 = _REG_BIT(0x1C, 17),
|
||||
RCC_I2C1 = _REG_BIT(0x1C, 21),
|
||||
RCC_I2C2 = _REG_BIT(0x1C, 22),
|
||||
RCC_USB = _REG_BIT(0x1C, 23),
|
||||
RCC_PWR = _REG_BIT(0x1C, 28),
|
||||
RCC_DAC = _REG_BIT(0x1C, 29),
|
||||
RCC_CEC = _REG_BIT(0x1C, 30),
|
||||
};
|
||||
|
||||
enum rcc_periph_rst {
|
||||
|
||||
/* Advanced peripherals */
|
||||
RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */
|
||||
|
||||
/* AHB peripherals */
|
||||
RST_GPIOA = _REG_BIT(0x28, 17),
|
||||
RST_GPIOB = _REG_BIT(0x28, 18),
|
||||
RST_GPIOC = _REG_BIT(0x28, 19),
|
||||
RST_GPIOD = _REG_BIT(0x28, 20),
|
||||
RST_GPIOE = _REG_BIT(0x28, 21),
|
||||
RST_GPIOF = _REG_BIT(0x28, 22),
|
||||
RST_TSC = _REG_BIT(0x28, 24),
|
||||
|
||||
/* APB2 peripherals */
|
||||
RST_SYSCFG = _REG_BIT(0x0C, 0),
|
||||
RST_ADC = _REG_BIT(0x0C, 9),
|
||||
RST_TIM1 = _REG_BIT(0x0C, 11),
|
||||
RST_SPI1 = _REG_BIT(0x0C, 12),
|
||||
RST_USART1 = _REG_BIT(0x0C, 14),
|
||||
RST_TIM15 = _REG_BIT(0x0C, 16),
|
||||
RST_TIM16 = _REG_BIT(0x0C, 17),
|
||||
RST_TIM17 = _REG_BIT(0x0C, 18),
|
||||
|
||||
/* APB1 peripherals */
|
||||
RST_TIM2 = _REG_BIT(0x10, 0),
|
||||
RST_TIM3 = _REG_BIT(0x10, 1),
|
||||
RST_TIM6 = _REG_BIT(0x10, 4),
|
||||
RST_TIM14 = _REG_BIT(0x10, 8),
|
||||
RST_WWDG = _REG_BIT(0x10, 11),
|
||||
RST_SPI2 = _REG_BIT(0x10, 14),
|
||||
RST_SPI3 = _REG_BIT(0x10, 15),
|
||||
RST_USART2 = _REG_BIT(0x10, 17),
|
||||
RST_I2C1 = _REG_BIT(0x10, 21),
|
||||
RST_I2C2 = _REG_BIT(0x10, 22),
|
||||
RST_USB = _REG_BIT(0x10, 23),
|
||||
RST_PWR = _REG_BIT(0x10, 28),
|
||||
RST_DAC = _REG_BIT(0x10, 29),
|
||||
RST_CEC = _REG_BIT(0x10, 30),
|
||||
};
|
||||
|
||||
#include <libopencm3/stm32/common/rcc_common_all.h>
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void rcc_osc_ready_int_clear(enum rcc_osc osc);
|
||||
void rcc_osc_ready_int_enable(enum rcc_osc osc);
|
||||
void rcc_osc_ready_int_disable(enum rcc_osc osc);
|
||||
int rcc_osc_ready_int_flag(enum rcc_osc osc);
|
||||
void rcc_css_int_clear(void);
|
||||
int rcc_css_int_flag(void);
|
||||
void rcc_osc_on(enum rcc_osc osc);
|
||||
void rcc_osc_off(enum rcc_osc osc);
|
||||
void rcc_css_enable(void);
|
||||
void rcc_css_disable(void);
|
||||
void rcc_set_sysclk_source(uint32_t clk);
|
||||
void rcc_set_pll_multiplication_factor(uint32_t mul);
|
||||
void rcc_set_pll_source(uint32_t pllsrc);
|
||||
void rcc_set_pllxtpre(uint32_t pllxtpre);
|
||||
uint32_t rcc_rtc_clock_enabled_flag(void);
|
||||
void rcc_enable_rtc_clock(void);
|
||||
void rcc_set_rtc_clock_source(enum rcc_osc clock_source);
|
||||
void rcc_set_adcpre(uint32_t adcpre);
|
||||
void rcc_set_ppre2(uint32_t ppre1);
|
||||
void rcc_set_ppre1(uint32_t ppre1);
|
||||
void rcc_set_hpre(uint32_t hpre);
|
||||
void rcc_set_usbpre(uint32_t usbpre);
|
||||
void rcc_set_prediv(uint32_t prediv);
|
||||
uint32_t rcc_system_clock_source(void);
|
||||
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock);
|
||||
void rcc_backupdomain_reset(void);
|
||||
|
||||
END_DECLS
|
||||
|
||||
#endif
|
||||
/**@}*/
|
||||
|
||||
28
include/libopencm3/gd32/flash.h
Normal file
28
include/libopencm3/gd32/flash.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/* This provides unification of code over GD32 subfamilies */
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/gd32/memorymap.h>
|
||||
|
||||
#if defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/flash.h>
|
||||
#else
|
||||
# error "gd32 family not defined."
|
||||
#endif
|
||||
|
||||
28
include/libopencm3/gd32/gpio.h
Normal file
28
include/libopencm3/gd32/gpio.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/* This provides unification of code over GD32 subfamilies */
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/gd32/memorymap.h>
|
||||
|
||||
#if defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/gpio.h>
|
||||
#else
|
||||
# error "gd32 family not defined."
|
||||
#endif
|
||||
|
||||
29
include/libopencm3/gd32/memorymap.h
Normal file
29
include/libopencm3/gd32/memorymap.h
Normal file
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H
|
||||
#define LIBOPENCM3_MEMORYMAP_COMMON_H
|
||||
|
||||
#if defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/memorymap.h>
|
||||
#else
|
||||
# error "gd32 family not defined."
|
||||
#endif
|
||||
|
||||
#endif /* LIBOPENCM3_MEMORYMAP_COMMON_H */
|
||||
28
include/libopencm3/gd32/rcc.h
Normal file
28
include/libopencm3/gd32/rcc.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/* This provides unification of code over GD32 subfamilies */
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/gd32/memorymap.h>
|
||||
|
||||
#if defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/rcc.h>
|
||||
#else
|
||||
# error "gd32 family not defined."
|
||||
#endif
|
||||
|
||||
@@ -38,6 +38,8 @@
|
||||
# include <libopencm3/stm32/l1/flash.h>
|
||||
#elif defined(STM32L4)
|
||||
# include <libopencm3/stm32/l4/flash.h>
|
||||
#elif defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/flash.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
|
||||
@@ -38,6 +38,8 @@
|
||||
# include <libopencm3/stm32/l1/gpio.h>
|
||||
#elif defined(STM32L4)
|
||||
# include <libopencm3/stm32/l4/gpio.h>
|
||||
#elif defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/gpio.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
|
||||
@@ -38,6 +38,8 @@
|
||||
# include <libopencm3/stm32/l1/memorymap.h>
|
||||
#elif defined(STM32L4)
|
||||
# include <libopencm3/stm32/l4/memorymap.h>
|
||||
#elif defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/memorymap.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
|
||||
@@ -38,6 +38,8 @@
|
||||
# include <libopencm3/stm32/l1/rcc.h>
|
||||
#elif defined(STM32L4)
|
||||
# include <libopencm3/stm32/l4/rcc.h>
|
||||
#elif defined(GD32F1X0)
|
||||
# include <libopencm3/gd32/f1x0/rcc.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
|
||||
@@ -17,6 +17,9 @@
|
||||
#elif defined(STM32L4)
|
||||
# include <libopencmsis/stm32/l4/irqhandlers.h>
|
||||
|
||||
#elif defined(GD32F1X0)
|
||||
# include <libopencmsis/gd32/f1x0/irqhandlers.h>
|
||||
|
||||
#elif defined(EFM32TG)
|
||||
# include <libopencmsis/efm32/efm32tg/irqhandlers.h>
|
||||
#elif defined(EFM32G)
|
||||
|
||||
60
include/libopencmsis/gd32/f1x0/irqhandlers.h
Normal file
60
include/libopencmsis/gd32/f1x0/irqhandlers.h
Normal file
@@ -0,0 +1,60 @@
|
||||
/* This file is part of the libopencm3 project.
|
||||
*
|
||||
* It was generated by the irq2nvic_h script.
|
||||
*
|
||||
* These definitions bend every interrupt handler that is defined CMSIS style
|
||||
* to the weak symbol exported by libopencm3.
|
||||
*/
|
||||
|
||||
#define WWDG_IRQHandler wwdg_isr
|
||||
#define PVD_IRQHandler pvd_isr
|
||||
#define RTC_IRQHandler rtc_isr
|
||||
#define FLASH_IRQHandler flash_isr
|
||||
#define RCC_IRQHandler rcc_isr
|
||||
#define EXTI0_1_IRQHandler exti0_1_isr
|
||||
#define EXTI2_3_IRQHandler exti2_3_isr
|
||||
#define EXTI4_15_IRQHandler exti4_15_isr
|
||||
#define TSC_IRQHandler tsc_isr
|
||||
#define DMA_CHANNEL1_IRQHandler dma_channel1_isr
|
||||
#define DMA_CHANNEL2_3_IRQHandler dma_channel2_3_isr
|
||||
#define DMA_CHANNEL4_5_IRQHandler dma_channel4_5_isr
|
||||
#define ADC_COMP_IRQHandler adc_comp_isr
|
||||
#define TIM1_BRK_UP_TRG_COM_IRQHandler tim1_brk_up_trg_com_isr
|
||||
#define TIM1_CC_IRQHandler tim1_cc_isr
|
||||
#define TIM2_IRQHandler tim2_isr
|
||||
#define TIM3_IRQHandler tim3_isr
|
||||
#define TIM6_DAC_IRQHandler tim6_dac_isr
|
||||
#define RESERVED0_IRQHandler reserved0_isr
|
||||
#define TIM14_IRQHandler tim14_isr
|
||||
#define TIM15_IRQHandler tim15_isr
|
||||
#define TIM16_IRQHandler tim16_isr
|
||||
#define TIM17_IRQHandler tim17_isr
|
||||
#define I2C1_EV_IRQHandler i2c1_ev_isr
|
||||
#define I2C2_EV_IRQHandler i2c2_ev_isr
|
||||
#define SPI1_IRQHandler spi1_isr
|
||||
#define SPI2_IRQHandler spi2_isr
|
||||
#define USART1_IRQHandler usart1_isr
|
||||
#define USART2_IRQHandler usart2_isr
|
||||
#define RESERVED1_IRQHandler reserved1_isr
|
||||
#define CEC_CAN_IRQHandler cec_can_isr
|
||||
#define RESERVED2_IRQHandler reserved2_isr
|
||||
#define I2C1_ER_IRQHandler i2c1_er_isr
|
||||
#define RESERVED3_IRQHandler reserved3_isr
|
||||
#define I2C2_ER_IRQHandler i2c2_er_isr
|
||||
#define I2C3_EV_IRQHandler i2c3_ev_isr
|
||||
#define I2C3_ER_IRQHandler i2c3_er_isr
|
||||
#define USB_LP_IRQHandler usb_lp_isr
|
||||
#define USB_HP_IRQHandler usb_hp_isr
|
||||
#define RESERVED4_IRQHandler reserved4_isr
|
||||
#define RESERVED5_IRQHandler reserved5_isr
|
||||
#define RESERVED6_IRQHandler reserved6_isr
|
||||
#define USB_WAKEUP_IRQHandler usb_wakeup_isr
|
||||
#define RESERVED7_IRQHandler reserved7_isr
|
||||
#define RESERVED8_IRQHandler reserved8_isr
|
||||
#define RESERVED9_IRQHandler reserved9_isr
|
||||
#define RESERVED10_IRQHandler reserved10_isr
|
||||
#define RESERVED11_IRQHandler reserved11_isr
|
||||
#define DMA_CHANNEL6_7_IRQHandler dma_channel6_7_isr
|
||||
#define RESERVED12_IRQHandler reserved12_isr
|
||||
#define RESERVED13_IRQHandler reserved13_isr
|
||||
#define SPI3_IRQHandler spi3_isr
|
||||
Reference in New Issue
Block a user