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stm32g4: rcc: target stylecheck issues

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No functional change.

Signed-off-by: Benedikt Spranger <b.spranger@linutronix.de>
This commit is contained in:
Benedikt Spranger
2023-07-23 21:04:06 +02:00
committed by Piotr Esden-Tempski
parent 7742f1cfd6
commit f8b9b14f83
2 changed files with 15 additions and 13 deletions
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19
include/libopencm3/stm32/g4/rcc.h
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@@ -717,14 +717,14 @@
/** Enumerations for core system/bus clocks for user/driver/system access to base bus clocks /** Enumerations for core system/bus clocks for user/driver/system access to base bus clocks
* not directly associated with a peripheral. */ * not directly associated with a peripheral. */
enum rcc_clock_source { enum rcc_clock_source {
RCC_CPUCLK, RCC_CPUCLK,
RCC_SYSCLK, RCC_SYSCLK,
RCC_PERCLK, RCC_PERCLK,
RCC_SYSTICKCLK, RCC_SYSTICKCLK,
RCC_HCLK3, RCC_HCLK3,
RCC_AHBCLK, /* AHB1,2,4 all share base HCLK. */ RCC_AHBCLK, /* AHB1,2,4 all share base HCLK. */
RCC_APB1CLK, /* Note: APB1 and PCLK1 in manual */ RCC_APB1CLK, /* Note: APB1 and PCLK1 in manual */
RCC_APB2CLK, /* Note: APB2 and PCLK2 in manual */ RCC_APB2CLK, /* Note: APB2 and PCLK2 in manual */
}; };
/* --- Variable definitions ------------------------------------------------ */ /* --- Variable definitions ------------------------------------------------ */
@@ -1030,7 +1030,8 @@ void rcc_set_main_pll(uint32_t pllsrc, uint32_t pllm, uint32_t plln,
uint32_t pllp, uint32_t pllq, uint32_t pllr); uint32_t pllp, uint32_t pllq, uint32_t pllr);
uint32_t rcc_system_clock_source(void); uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); void rcc_clock_setup_pll(const struct rcc_clock_scale *clock);
void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement"))) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement")))
rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock);
void rcc_set_clock48_source(uint32_t clksel); void rcc_set_clock48_source(uint32_t clksel);
/** /**
* Get the peripheral clock speed for the specified (LP)UxART * Get the peripheral clock speed for the specified (LP)UxART

9
lib/stm32/g4/rcc.c
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@@ -639,11 +639,11 @@ void rcc_set_main_pll(uint32_t pllsrc, uint32_t pllm, uint32_t plln,
RCC_PLLCFGR = ((pllsrc & RCC_PLLCFGR_PLLSRC_MASK) << RCC_PLLCFGR_PLLSRC_SHIFT) | RCC_PLLCFGR = ((pllsrc & RCC_PLLCFGR_PLLSRC_MASK) << RCC_PLLCFGR_PLLSRC_SHIFT) |
((pllm & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_SHIFT) | ((pllm & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_SHIFT) |
((plln & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_SHIFT) | ((plln & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_SHIFT) |
(pllpen ? RCC_PLLCFGR_PLLPEN : 0 ) | (pllpen ? RCC_PLLCFGR_PLLPEN : 0) |
(pllp ? RCC_PLLCFGR_PLLP_DIV17 : RCC_PLLCFGR_PLLP_DIV7) | (pllp ? RCC_PLLCFGR_PLLP_DIV17 : RCC_PLLCFGR_PLLP_DIV7) |
(pllqen ? RCC_PLLCFGR_PLLQEN : 0 ) | (pllqen ? RCC_PLLCFGR_PLLQEN : 0) |
((pllq & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_SHIFT) | ((pllq & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_SHIFT) |
(pllren ? RCC_PLLCFGR_PLLREN : 0 ) | (pllren ? RCC_PLLCFGR_PLLREN : 0) |
((pllr & RCC_PLLCFGR_PLLR_MASK) << RCC_PLLCFGR_PLLR_SHIFT) | ((pllr & RCC_PLLCFGR_PLLR_MASK) << RCC_PLLCFGR_PLLR_SHIFT) |
((pllpdiv & RCC_PLLCFGR_PLLPDIV_MASK) << RCC_PLLCFGR_PLLPDIV_SHIFT); ((pllpdiv & RCC_PLLCFGR_PLLPDIV_MASK) << RCC_PLLCFGR_PLLPDIV_SHIFT);
} }
@@ -763,7 +763,8 @@ void rcc_set_clock48_source(uint32_t clksel)
RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT); RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT);
} }
static uint32_t rcc_get_clksel_freq(uint8_t shift) { static uint32_t rcc_get_clksel_freq(uint8_t shift)
{
uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_SEL_MASK; uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_SEL_MASK;
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK; uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
switch (clksel) { switch (clksel) {