From f8b9b14f83e94031e8bed846dc270f6e04241267 Mon Sep 17 00:00:00 2001 From: Benedikt Spranger Date: Sun, 23 Jul 2023 21:04:06 +0200 Subject: [PATCH] stm32g4: rcc: target stylecheck issues No functional change. Signed-off-by: Benedikt Spranger --- include/libopencm3/stm32/g4/rcc.h | 19 ++++++++++--------- lib/stm32/g4/rcc.c | 9 +++++---- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/include/libopencm3/stm32/g4/rcc.h b/include/libopencm3/stm32/g4/rcc.h index bc50f413..b1acf9fc 100644 --- a/include/libopencm3/stm32/g4/rcc.h +++ b/include/libopencm3/stm32/g4/rcc.h @@ -717,14 +717,14 @@ /** Enumerations for core system/bus clocks for user/driver/system access to base bus clocks * not directly associated with a peripheral. */ enum rcc_clock_source { - RCC_CPUCLK, - RCC_SYSCLK, - RCC_PERCLK, - RCC_SYSTICKCLK, - RCC_HCLK3, - RCC_AHBCLK, /* AHB1,2,4 all share base HCLK. */ - RCC_APB1CLK, /* Note: APB1 and PCLK1 in manual */ - RCC_APB2CLK, /* Note: APB2 and PCLK2 in manual */ + RCC_CPUCLK, + RCC_SYSCLK, + RCC_PERCLK, + RCC_SYSTICKCLK, + RCC_HCLK3, + RCC_AHBCLK, /* AHB1,2,4 all share base HCLK. */ + RCC_APB1CLK, /* Note: APB1 and PCLK1 in manual */ + RCC_APB2CLK, /* Note: APB2 and PCLK2 in manual */ }; /* --- Variable definitions ------------------------------------------------ */ @@ -1030,7 +1030,8 @@ void rcc_set_main_pll(uint32_t pllsrc, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr); uint32_t rcc_system_clock_source(void); void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); -void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement"))) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); +void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement"))) + rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); void rcc_set_clock48_source(uint32_t clksel); /** * Get the peripheral clock speed for the specified (LP)UxART diff --git a/lib/stm32/g4/rcc.c b/lib/stm32/g4/rcc.c index b54217c0..5d234c61 100644 --- a/lib/stm32/g4/rcc.c +++ b/lib/stm32/g4/rcc.c @@ -639,11 +639,11 @@ void rcc_set_main_pll(uint32_t pllsrc, uint32_t pllm, uint32_t plln, RCC_PLLCFGR = ((pllsrc & RCC_PLLCFGR_PLLSRC_MASK) << RCC_PLLCFGR_PLLSRC_SHIFT) | ((pllm & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_SHIFT) | ((plln & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_SHIFT) | - (pllpen ? RCC_PLLCFGR_PLLPEN : 0 ) | + (pllpen ? RCC_PLLCFGR_PLLPEN : 0) | (pllp ? RCC_PLLCFGR_PLLP_DIV17 : RCC_PLLCFGR_PLLP_DIV7) | - (pllqen ? RCC_PLLCFGR_PLLQEN : 0 ) | + (pllqen ? RCC_PLLCFGR_PLLQEN : 0) | ((pllq & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_SHIFT) | - (pllren ? RCC_PLLCFGR_PLLREN : 0 ) | + (pllren ? RCC_PLLCFGR_PLLREN : 0) | ((pllr & RCC_PLLCFGR_PLLR_MASK) << RCC_PLLCFGR_PLLR_SHIFT) | ((pllpdiv & RCC_PLLCFGR_PLLPDIV_MASK) << RCC_PLLCFGR_PLLPDIV_SHIFT); } @@ -763,7 +763,8 @@ void rcc_set_clock48_source(uint32_t clksel) RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT); } -static uint32_t rcc_get_clksel_freq(uint8_t shift) { +static uint32_t rcc_get_clksel_freq(uint8_t shift) +{ uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_SEL_MASK; uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK; switch (clksel) {