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stm32g4: Implement RCC

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Co-authored-by: Sam Kirkham <sam.kirkham@codethink.co.uk>
This commit is contained in:
Ben Brewer
2020-11-30 12:57:43 +00:00
committed by Karl Palsson
parent 59569bfb04
commit f4f75c92dd
3 changed files with 1084 additions and 215 deletions
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531
include/libopencm3/stm32/g4/rcc.h
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@@ -8,6 +8,8 @@
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2020 Karl Palsson <karlp@tweak.net.au>
* @author @htmlonly &copy; @endhtmlonly 2020 Sam Kirkham <sam.kirkham@codethink.co.uk>
* @author @htmlonly &copy; @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* LGPL License Terms @ref lgpl_license
*/
@@ -16,6 +18,8 @@
* This file is part of the libopencm3 project.
*
* Copyright (C) 2020 Karl Palsson <karlp@tweak.net.au>
* Copyright (C) 2020 Sam Kirkham <sam.kirkham@codethink.co.uk>
* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -37,6 +41,8 @@
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
#include <libopencm3/stm32/pwr.h>
/** @defgroup rcc_registers RCC Registers
* @{
*/
@@ -47,24 +53,42 @@
#define RCC_CIER MMIO32(RCC_BASE + 0x18)
#define RCC_CIFR MMIO32(RCC_BASE + 0x1c)
#define RCC_CICR MMIO32(RCC_BASE + 0x20)
#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x28)
#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x2c)
#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x30)
#define RCC_APB1RSTR1 MMIO32(RCC_BASE + 0x38)
#define RCC_APB1RSTR2 MMIO32(RCC_BASE + 0x3c)
#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x40)
#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x48)
#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x4c)
#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x50)
#define RCC_APB1ENR1 MMIO32(RCC_BASE + 0x58)
#define RCC_APB1ENR2 MMIO32(RCC_BASE + 0x5c)
#define RCC_APB2ENR MMIO32(RCC_BASE + 0x60)
#define RCC_AHB1SMENR MMIO32(RCC_BASE + 0x68)
#define RCC_AHB2SMENR MMIO32(RCC_BASE + 0x6c)
#define RCC_AHB3SMENR MMIO32(RCC_BASE + 0x70)
#define RCC_APB1SMENR1 MMIO32(RCC_BASE + 0x78)
#define RCC_APB1SMENR2 MMIO32(RCC_BASE + 0x7c)
#define RCC_APB2SMENR MMIO32(RCC_BASE + 0x80)
#define RCC_AHB1RSTR_OFFSET 0x28
#define RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)
#define RCC_AHB2RSTR_OFFSET 0x2c
#define RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)
#define RCC_AHB3RSTR_OFFSET 0x30
#define RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)
#define RCC_APB1RSTR1_OFFSET 0x38
#define RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)
#define RCC_APB1RSTR2_OFFSET 0x3c
#define RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)
#define RCC_APB2RSTR_OFFSET 0x40
#define RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)
#define RCC_AHB1ENR_OFFSET 0x48
#define RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)
#define RCC_AHB2ENR_OFFSET 0x4c
#define RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)
#define RCC_AHB3ENR_OFFSET 0x50
#define RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)
#define RCC_APB1ENR1_OFFSET 0x58
#define RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)
#define RCC_APB1ENR2_OFFSET 0x5c
#define RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)
#define RCC_APB2ENR_OFFSET 0x60
#define RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)
#define RCC_AHB1SMENR_OFFSET 0x68
#define RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)
#define RCC_AHB2SMENR_OFFSET 0x6c
#define RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)
#define RCC_AHB3SMENR_OFFSET 0x70
#define RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)
#define RCC_APB1SMENR1_OFFSET 0x78
#define RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)
#define RCC_APB1SMENR2_OFFSET 0x7c
#define RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)
#define RCC_APB2SMENR_OFFSET 0x80
#define RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)
#define RCC_CCIPR MMIO32(RCC_BASE + 0x88)
#define RCC_BDCR MMIO32(RCC_BASE + 0x90)
#define RCC_CSR MMIO32(RCC_BASE + 0x94)
@@ -91,7 +115,7 @@
* @{
*/
#define RCC_ICSCR_HSITRIM_SHIFT 24
#define RCC_ICSCR_HSITRIM_MASK 0x1f
#define RCC_ICSCR_HSITRIM_MASK 0x7f
#define RCC_ICSCR_HSICAL_SHIFT 16
#define RCC_ICSCR_HSICAL_MASK 0xff
/**@}*/
@@ -173,9 +197,12 @@
/** @defgroup rcc_pllcfgr_values RCC_PLLCFGR - PLL Configuration Register
* @{
*/
#define RCC_CFGR_PLLPDIV_MASK 0x1f
#define RCC_CFGR_PLLPDIV_SHIFT 27
#define RCC_PLLCFGR_PLLPDIV_MASK 0x1f
#define RCC_PLLCFGR_PLLPDIV_SHIFT 27
/** @defgroup rcc_pllcfgr_pllr RCC_PLLCFGR PLLR values
* Set these bits correctly not to exceed 170 MHz on this domain.
* @{*/
#define RCC_PLLCFGR_PLLR_DIV2 0
#define RCC_PLLCFGR_PLLR_DIV4 1
#define RCC_PLLCFGR_PLLR_DIV6 2
@@ -198,17 +225,17 @@
#define RCC_PLLCFGR_PLLP BIT17
#define RCC_PLLCFGR_PLLP_DIV7 0
#define RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP
#define RCC_PLLPEN (1 << 16)
#define RCC_PLLCFGR_PLLPEN (1 << 16)
/** @defgroup rcc_pllcfgr_plln RCC_PLLCFGR PLLN values
* Allowed values 8 <= n <= 127, VCO output between 64 and 344 MHz
* Allowed values 8 <= n <= 127, VCO output limits specified in datasheet
* @{*/
#define RCC_PLLCFGR_PLLN_SHIFT 8
#define RCC_PLLCFGR_PLLN_MASK 0x7f
/**@}*/
/** @defgroup rcc_pllcfgr_pllm RCC_PLLCFGR PLLM values
* Allowed values 1 <= m <= 16, VCO input between 2.66 and 8 MHz
* Allowed values 1 <= m <= 16, VCO input limits specified in datasheet
* @{*/
#define RCC_PLLCFGR_PLLM_SHIFT 0x4
#define RCC_PLLCFGR_PLLM_MASK 0xf
@@ -270,7 +297,7 @@
#define RCC_AHB1RSTR_CRCRST (1 << 12)
#define RCC_AHB1RSTR_FLASHRST (1 << 8)
#define RCC_AHB1RSTR_FMACRST (1 << 4)
#define RCC_AHB1RSTR_CORDIC2RST (1 << 3)
#define RCC_AHB1RSTR_CORDICRST (1 << 3)
#define RCC_AHB1RSTR_DMAMUX1RST (1 << 2)
#define RCC_AHB1RSTR_DMA2RST (1 << 1)
#define RCC_AHB1RSTR_DMA1RST (1 << 0)
@@ -612,6 +639,8 @@
/** defgroup rcc_ccipr2_values RCC_CCIPR2 - Peripherals independent clock config register 2
* @{
*/
#define RCC_CCIPR2_SEL_MASK 0x3
#define RCC_CCIPR2_QSPI_SYS 0
#define RCC_CCIPR2_QSPI_HSI16 1
#define RCC_CCIPR2_QSPI_PLLQ 2
@@ -683,6 +712,19 @@
#define RCC_CRRCR_HSI48ON BIT0
/**@}*/
/** Enumerations for core system/bus clocks for user/driver/system access to base bus clocks
* not directly associated with a peripheral. */
enum rcc_clock_source {
RCC_CPUCLK,
RCC_SYSCLK,
RCC_PERCLK,
RCC_SYSTICKCLK,
RCC_HCLK3,
RCC_AHBCLK, /* AHB1,2,4 all share base HCLK. */
RCC_APB1CLK, /* Note: APB1 and PCLK1 in manual */
RCC_APB2CLK, /* Note: APB2 and PCLK2 in manual */
};
/* --- Variable definitions ------------------------------------------------ */
extern uint32_t rcc_ahb_frequency;
@@ -691,242 +733,303 @@ extern uint32_t rcc_apb2_frequency;
/* --- Function prototypes ------------------------------------------------- */
enum rcc_osc {
RCC_PLL, RCC_HSE, RCC_HSI16, RCC_LSE, RCC_LSI, RCC_HSI48
enum rcc_clock_3v3 {
RCC_CLOCK_3V3_24MHZ,
RCC_CLOCK_3V3_48MHZ,
RCC_CLOCK_3V3_96MHZ,
RCC_CLOCK_3V3_170MHZ,
RCC_CLOCK_3V3_END
};
struct rcc_clock_scale {
uint8_t pllm;
uint16_t plln;
uint8_t pllp;
uint8_t pllq;
uint8_t pllr;
uint8_t pll_source;
uint8_t hpre;
uint8_t ppre1;
uint8_t ppre2;
enum pwr_vos_scale vos_scale;
bool boost;
uint32_t flash_config;
uint8_t flash_waitstates;
uint32_t ahb_frequency;
uint32_t apb1_frequency;
uint32_t apb2_frequency;
};
extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END];
extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END];
extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END];
extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END];
enum rcc_osc {
RCC_HSI48,
RCC_PLL,
RCC_HSE,
RCC_HSI16,
RCC_LSE,
RCC_LSI
};
#define _REG_BIT(base, bit) (((base) << 5) + (bit))
enum rcc_periph_clken {
/* AHB1 peripherals */
RCC_CRC = _REG_BIT(0x48, 12),
RCC_FLASH = _REG_BIT(0x48, 8),
RCC_FMAC = _REG_BIT(0x48, 4),
RCC_CORDIC = _REG_BIT(0x48, 3),
RCC_DMAMUX1 = _REG_BIT(0x48, 2),
RCC_DMA2 = _REG_BIT(0x48, 1),
RCC_DMA1 = _REG_BIT(0x48, 0),
RCC_CRC = _REG_BIT(RCC_AHB1ENR_OFFSET, 12),
RCC_FLASH = _REG_BIT(RCC_AHB1ENR_OFFSET, 8),
RCC_FMAC = _REG_BIT(RCC_AHB1ENR_OFFSET, 4),
RCC_CORDIC = _REG_BIT(RCC_AHB1ENR_OFFSET, 3),
RCC_DMAMUX1 = _REG_BIT(RCC_AHB1ENR_OFFSET, 2),
RCC_DMA2 = _REG_BIT(RCC_AHB1ENR_OFFSET, 1),
RCC_DMA1 = _REG_BIT(RCC_AHB1ENR_OFFSET, 0),
/* AHB2 peripherals */
RCC_RNG = _REG_BIT(0x4c, 26),
RCC_AES = _REG_BIT(0x4c, 24),
RCC_DAC4 = _REG_BIT(0x4c, 19),
RCC_DAC3 = _REG_BIT(0x4c, 18),
RCC_DAC2 = _REG_BIT(0x4c, 17),
RCC_DAC1 = _REG_BIT(0x4c, 16),
RCC_ADC345 = _REG_BIT(0x4c, 14),
RCC_ADC12 = _REG_BIT(0x4c, 13),
RCC_ADC1 = _REG_BIT(0x4c, 13), /* Compatibility */
RCC_GPIOG = _REG_BIT(0x4c, 6),
RCC_GPIOF = _REG_BIT(0x4c, 5),
RCC_GPIOE = _REG_BIT(0x4c, 4),
RCC_GPIOD = _REG_BIT(0x4c, 3),
RCC_GPIOC = _REG_BIT(0x4c, 2),
RCC_GPIOB = _REG_BIT(0x4c, 1),
RCC_GPIOA = _REG_BIT(0x4c, 0),
RCC_RNG = _REG_BIT(RCC_AHB2ENR_OFFSET, 26),
RCC_AES = _REG_BIT(RCC_AHB2ENR_OFFSET, 24),
RCC_DAC4 = _REG_BIT(RCC_AHB2ENR_OFFSET, 19),
RCC_DAC3 = _REG_BIT(RCC_AHB2ENR_OFFSET, 18),
RCC_DAC2 = _REG_BIT(RCC_AHB2ENR_OFFSET, 17),
RCC_DAC1 = _REG_BIT(RCC_AHB2ENR_OFFSET, 16),
RCC_ADC345 = _REG_BIT(RCC_AHB2ENR_OFFSET, 14),
RCC_ADC12 = _REG_BIT(RCC_AHB2ENR_OFFSET, 13),
RCC_ADC1 = _REG_BIT(RCC_AHB2ENR_OFFSET, 13), /* Compatibility */
RCC_GPIOG = _REG_BIT(RCC_AHB2ENR_OFFSET, 6),
RCC_GPIOF = _REG_BIT(RCC_AHB2ENR_OFFSET, 5),
RCC_GPIOE = _REG_BIT(RCC_AHB2ENR_OFFSET, 4),
RCC_GPIOD = _REG_BIT(RCC_AHB2ENR_OFFSET, 3),
RCC_GPIOC = _REG_BIT(RCC_AHB2ENR_OFFSET, 2),
RCC_GPIOB = _REG_BIT(RCC_AHB2ENR_OFFSET, 1),
RCC_GPIOA = _REG_BIT(RCC_AHB2ENR_OFFSET, 0),
/* AHB3 peripherals */
RCC_QSPI = _REG_BIT(0x50, 8),
RCC_FMC = _REG_BIT(0x50, 0),
RCC_QSPI = _REG_BIT(RCC_AHB3ENR_OFFSET, 8),
RCC_FMC = _REG_BIT(RCC_AHB3ENR_OFFSET, 0),
/* APB1 peripherals */
RCC_LPTIM1 = _REG_BIT(0x58, 31),
RCC_I2C3 = _REG_BIT(0x58, 30),
RCC_PWR = _REG_BIT(0x58, 28),
RCC_FDCAN = _REG_BIT(0x58, 25),
RCC_USB = _REG_BIT(0x58, 23),
RCC_I2C2 = _REG_BIT(0x58, 22),
RCC_I2C1 = _REG_BIT(0x58, 21),
RCC_UART5 = _REG_BIT(0x58, 20),
RCC_UART4 = _REG_BIT(0x58, 19),
RCC_USART3 = _REG_BIT(0x58, 18),
RCC_USART2 = _REG_BIT(0x58, 17),
RCC_SPI3 = _REG_BIT(0x58, 15),
RCC_SPI2 = _REG_BIT(0x58, 14),
RCC_WWDG = _REG_BIT(0x58, 11),
RCC_RTCAPB = _REG_BIT(0x58, 10),
RCC_CRS = _REG_BIT(0x58, 8),
RCC_TIM7 = _REG_BIT(0x58, 5),
RCC_TIM6 = _REG_BIT(0x58, 4),
RCC_TIM5 = _REG_BIT(0x58, 3),
RCC_TIM4 = _REG_BIT(0x58, 2),
RCC_TIM3 = _REG_BIT(0x58, 1),
RCC_TIM2 = _REG_BIT(0x58, 0),
RCC_LPTIM1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 31),
RCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 30),
RCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28),
RCC_FDCAN = _REG_BIT(RCC_APB1ENR1_OFFSET, 25),
RCC_USB = _REG_BIT(RCC_APB1ENR1_OFFSET, 23),
RCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22),
RCC_I2C1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 21),
RCC_UART5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 20),
RCC_UART4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 19),
RCC_USART3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 18),
RCC_USART2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 17),
RCC_SPI3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 15),
RCC_SPI2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 14),
RCC_WWDG = _REG_BIT(RCC_APB1ENR1_OFFSET, 11),
RCC_RTCAPB = _REG_BIT(RCC_APB1ENR1_OFFSET, 10),
RCC_CRS = _REG_BIT(RCC_APB1ENR1_OFFSET, 8),
RCC_TIM7 = _REG_BIT(RCC_APB1ENR1_OFFSET, 5),
RCC_TIM6 = _REG_BIT(RCC_APB1ENR1_OFFSET, 4),
RCC_TIM5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 3),
RCC_TIM4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 2),
RCC_TIM3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 1),
RCC_TIM2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 0),
/* apb1-2 */
RCC_UCPD1 = _REG_BIT(0x5c, 8),
RCC_I2C4 = _REG_BIT(0x5c, 1),
RCC_LPUART1 = _REG_BIT(0x5c, 0),
RCC_UCPD1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 8),
RCC_I2C4 = _REG_BIT(RCC_APB1ENR2_OFFSET, 1),
RCC_LPUART1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 0),
/* APB2 peripherals */
RCC_HRTIM1 = _REG_BIT(0x60, 26),
RCC_SAI1 = _REG_BIT(0x60, 21),
RCC_TIM20 = _REG_BIT(0x60, 20),
RCC_TIM17 = _REG_BIT(0x60, 18),
RCC_TIM16 = _REG_BIT(0x60, 17),
RCC_TIM15 = _REG_BIT(0x60, 16),
RCC_SPI4 = _REG_BIT(0x60, 15),
RCC_USART1 = _REG_BIT(0x60, 14),
RCC_TIM8 = _REG_BIT(0x60, 13),
RCC_SPI1 = _REG_BIT(0x60, 12),
RCC_TIM1 = _REG_BIT(0x60, 11),
RCC_SYSCFG = _REG_BIT(0x60, 0),
RCC_HRTIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 26),
RCC_SAI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 21),
RCC_TIM20 = _REG_BIT(RCC_APB2ENR_OFFSET, 20),
RCC_TIM17 = _REG_BIT(RCC_APB2ENR_OFFSET, 18),
RCC_TIM16 = _REG_BIT(RCC_APB2ENR_OFFSET, 17),
RCC_TIM15 = _REG_BIT(RCC_APB2ENR_OFFSET, 16),
RCC_SPI4 = _REG_BIT(RCC_APB2ENR_OFFSET, 15),
RCC_USART1 = _REG_BIT(RCC_APB2ENR_OFFSET, 14),
RCC_TIM8 = _REG_BIT(RCC_APB2ENR_OFFSET, 13),
RCC_SPI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 12),
RCC_TIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 11),
RCC_SYSCFG = _REG_BIT(RCC_APB2ENR_OFFSET, 0),
/* AHB1 peripherals in sleep mode */
SCC_CRC = _REG_BIT(0x68, 12),
SCC_SRAM1 = _REG_BIT(0x68, 9),
SCC_FLASH = _REG_BIT(0x68, 8),
SCC_FMAC = _REG_BIT(0x68, 4),
SCC_CORDIC = _REG_BIT(0x68, 3),
SCC_DMAMUX1 = _REG_BIT(0x68, 2),
SCC_DMA2 = _REG_BIT(0x68, 1),
SCC_DMA1 = _REG_BIT(0x68, 0),
SCC_CRC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 12),
SCC_SRAM1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 9),
SCC_FLASH = _REG_BIT(RCC_AHB1SMENR_OFFSET, 8),
SCC_FMAC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 4),
SCC_CORDIC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 3),
SCC_DMAMUX1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 2),
SCC_DMA2 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 1),
SCC_DMA1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 0),
/* AHB2 peripherals in sleep mode */
SCC_RNG = _REG_BIT(0x6c, 26),
SCC_AES = _REG_BIT(0x6c, 24),
SCC_DAC4 = _REG_BIT(0x6c, 19),
SCC_DAC3 = _REG_BIT(0x6c, 18),
SCC_DAC2 = _REG_BIT(0x6c, 17),
SCC_DAC1 = _REG_BIT(0x6c, 16),
SCC_ADC345 = _REG_BIT(0x6c, 14),
SCC_ADC12 = _REG_BIT(0x6c, 13),
SCC_ADC1 = _REG_BIT(0x6c, 13), /* Compatibility */
SCC_CCMSRAM = _REG_BIT(0x6c, 10),
SCC_SRAM2 = _REG_BIT(0x6c, 9),
SCC_GPIOG = _REG_BIT(0x6c, 6),
SCC_GPIOF = _REG_BIT(0x6c, 5),
SCC_GPIOE = _REG_BIT(0x6c, 4),
SCC_GPIOD = _REG_BIT(0x6c, 3),
SCC_GPIOC = _REG_BIT(0x6c, 2),
SCC_GPIOB = _REG_BIT(0x6c, 1),
SCC_GPIOA = _REG_BIT(0x6c, 0),
SCC_RNG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 26),
SCC_AES = _REG_BIT(RCC_AHB2SMENR_OFFSET, 24),
SCC_DAC4 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 19),
SCC_DAC3 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 18),
SCC_DAC2 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 17),
SCC_DAC1 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 16),
SCC_ADC345 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 14),
SCC_ADC12 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13),
SCC_ADC1 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13), /* Compatibility */
SCC_CCMSRAM = _REG_BIT(RCC_AHB2SMENR_OFFSET, 10),
SCC_SRAM2 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 9),
SCC_GPIOG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 6),
SCC_GPIOF = _REG_BIT(RCC_AHB2SMENR_OFFSET, 5),
SCC_GPIOE = _REG_BIT(RCC_AHB2SMENR_OFFSET, 4),
SCC_GPIOD = _REG_BIT(RCC_AHB2SMENR_OFFSET, 3),
SCC_GPIOC = _REG_BIT(RCC_AHB2SMENR_OFFSET, 2),
SCC_GPIOB = _REG_BIT(RCC_AHB2SMENR_OFFSET, 1),
SCC_GPIOA = _REG_BIT(RCC_AHB2SMENR_OFFSET, 0),
/* AHB3 peripherals in sleep mode */
SCC_QSPI = _REG_BIT(0x70, 8),
SCC_FMC = _REG_BIT(0x70, 0),
SCC_QSPI = _REG_BIT(RCC_AHB3SMENR_OFFSET, 8),
SCC_FMC = _REG_BIT(RCC_AHB3SMENR_OFFSET, 0),
/* APB1 peripherals in sleep mode */
SCC_LPTIM1 = _REG_BIT(0x58, 31),
SCC_I2C3 = _REG_BIT(0x58, 30),
SCC_PWR = _REG_BIT(0x58, 28),
SCC_FDCAN = _REG_BIT(0x58, 25),
SCC_USB = _REG_BIT(0x58, 23),
SCC_I2C2 = _REG_BIT(0x58, 22),
SCC_I2C1 = _REG_BIT(0x58, 21),
SCC_UART5 = _REG_BIT(0x58, 20),
SCC_UART4 = _REG_BIT(0x58, 19),
SCC_USART3 = _REG_BIT(0x58, 18),
SCC_USART2 = _REG_BIT(0x58, 17),
SCC_SPI3 = _REG_BIT(0x58, 15),
SCC_SPI2 = _REG_BIT(0x58, 14),
SCC_WWDG = _REG_BIT(0x58, 11),
SCC_RTCAPB = _REG_BIT(0x58, 10),
SCC_CRS = _REG_BIT(0x58, 8),
SCC_TIM7 = _REG_BIT(0x58, 5),
SCC_TIM6 = _REG_BIT(0x58, 4),
SCC_TIM5 = _REG_BIT(0x58, 3),
SCC_TIM4 = _REG_BIT(0x58, 2),
SCC_TIM3 = _REG_BIT(0x58, 1),
SCC_TIM2 = _REG_BIT(0x58, 0),
SCC_LPTIM1 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 31),
SCC_I2C3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 30),
SCC_PWR = _REG_BIT(RCC_APB1SMENR1_OFFSET, 28),
SCC_FDCAN = _REG_BIT(RCC_APB1SMENR1_OFFSET, 25),
SCC_USB = _REG_BIT(RCC_APB1SMENR1_OFFSET, 23),
SCC_I2C2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 22),
SCC_I2C1 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 21),
SCC_UART5 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 20),
SCC_UART4 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 19),
SCC_USART3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 18),
SCC_USART2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 17),
SCC_SPI3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 15),
SCC_SPI2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 14),
SCC_WWDG = _REG_BIT(RCC_APB1SMENR1_OFFSET, 11),
SCC_RTCAPB = _REG_BIT(RCC_APB1SMENR1_OFFSET, 10),
SCC_CRS = _REG_BIT(RCC_APB1SMENR1_OFFSET, 8),
SCC_TIM7 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 5),
SCC_TIM6 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 4),
SCC_TIM5 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 3),
SCC_TIM4 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 2),
SCC_TIM3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 1),
SCC_TIM2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 0),
/* apb1-2 */
SCC_UCPD1 = _REG_BIT(0x5c, 8),
SCC_I2C4 = _REG_BIT(0x5c, 1),
SCC_LPUART1 = _REG_BIT(0x5c, 0),
SCC_UCPD1 = _REG_BIT(RCC_APB1SMENR2_OFFSET, 8),
SCC_I2C4 = _REG_BIT(RCC_APB1SMENR2_OFFSET, 1),
SCC_LPUART1 = _REG_BIT(RCC_APB1SMENR2_OFFSET, 0),
/* APB2 peripherals in sleep mode */
SCC_HRTIM1 = _REG_BIT(0x60, 26),
SCC_SAI1 = _REG_BIT(0x60, 21),
SCC_TIM20 = _REG_BIT(0x60, 20),
SCC_TIM17 = _REG_BIT(0x60, 18),
SCC_TIM16 = _REG_BIT(0x60, 17),
SCC_TIM15 = _REG_BIT(0x60, 16),
SCC_SPI4 = _REG_BIT(0x60, 15),
SCC_USART1 = _REG_BIT(0x60, 14),
SCC_TIM8 = _REG_BIT(0x60, 13),
SCC_SPI1 = _REG_BIT(0x60, 12),
SCC_TIM1 = _REG_BIT(0x60, 11),
SCC_SYSCFG = _REG_BIT(0x60, 0),
SCC_HRTIM1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 26),
SCC_SAI1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 21),
SCC_TIM20 = _REG_BIT(RCC_APB2SMENR_OFFSET, 20),
SCC_TIM17 = _REG_BIT(RCC_APB2SMENR_OFFSET, 18),
SCC_TIM16 = _REG_BIT(RCC_APB2SMENR_OFFSET, 17),
SCC_TIM15 = _REG_BIT(RCC_APB2SMENR_OFFSET, 16),
SCC_SPI4 = _REG_BIT(RCC_APB2SMENR_OFFSET, 15),
SCC_USART1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 14),
SCC_TIM8 = _REG_BIT(RCC_APB2SMENR_OFFSET, 13),
SCC_SPI1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 12),
SCC_TIM1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 11),
SCC_SYSCFG = _REG_BIT(RCC_APB2SMENR_OFFSET, 0),
};
enum rcc_periph_rst {
/* AHB1 peripherals */
RST_CRC = _REG_BIT(0x28, 12),
RST_FLASH = _REG_BIT(0x28, 8),
RST_FMAC = _REG_BIT(0x28, 4),
RST_CORDIC = _REG_BIT(0x28, 3),
RST_DMAMUX1 = _REG_BIT(0x28, 2),
RST_DMA2 = _REG_BIT(0x28, 1),
RST_DMA1 = _REG_BIT(0x28, 0),
RST_CRC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 12),
RST_FLASH = _REG_BIT(RCC_AHB1RSTR_OFFSET, 8),
RST_FMAC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 4),
RST_CORDIC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 3),
RST_DMAMUX1 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 2),
RST_DMA2 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 1),
RST_DMA1 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 0),
/* AHB2 peripherals */
RST_RNG = _REG_BIT(0x2c, 26),
RST_AES = _REG_BIT(0x2c, 24),
RST_DAC4 = _REG_BIT(0x2c, 19),
RST_DAC3 = _REG_BIT(0x2c, 18),
RST_DAC2 = _REG_BIT(0x2c, 17),
RST_DAC1 = _REG_BIT(0x2c, 16),
RST_ADC345 = _REG_BIT(0x2c, 14),
RST_ADC12 = _REG_BIT(0x2c, 13),
RST_ADC1 = _REG_BIT(0x2c, 13), /* Compatibility */
RST_GPIOG = _REG_BIT(0x2c, 6),
RST_GPIOF = _REG_BIT(0x2c, 5),
RST_GPIOE = _REG_BIT(0x2c, 4),
RST_GPIOD = _REG_BIT(0x2c, 3),
RST_GPIOC = _REG_BIT(0x2c, 2),
RST_GPIOB = _REG_BIT(0x2c, 1),
RST_GPIOA = _REG_BIT(0x2c, 0),
RST_RNG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 26),
RST_AES = _REG_BIT(RCC_AHB2RSTR_OFFSET, 24),
RST_DAC4 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 19),
RST_DAC3 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 18),
RST_DAC2 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 17),
RST_DAC1 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 16),
RST_ADC345 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 14),
RST_ADC12 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13),
RST_ADC1 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13), /* Compatibility */
RST_GPIOG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 6),
RST_GPIOF = _REG_BIT(RCC_AHB2RSTR_OFFSET, 5),
RST_GPIOE = _REG_BIT(RCC_AHB2RSTR_OFFSET, 4),
RST_GPIOD = _REG_BIT(RCC_AHB2RSTR_OFFSET, 3),
RST_GPIOC = _REG_BIT(RCC_AHB2RSTR_OFFSET, 2),
RST_GPIOB = _REG_BIT(RCC_AHB2RSTR_OFFSET, 1),
RST_GPIOA = _REG_BIT(RCC_AHB2RSTR_OFFSET, 0),
/* AHB3 peripherals */
RST_QSPI = _REG_BIT(0x30, 8),
RST_FMC = _REG_BIT(0x30, 0),
RST_QSPI = _REG_BIT(RCC_AHB3RSTR_OFFSET, 8),
RST_FMC = _REG_BIT(RCC_AHB3RSTR_OFFSET, 0),
/* APB1 peripherals */
RST_LPTIM1 = _REG_BIT(0x38, 31),
RST_I2C3 = _REG_BIT(0x38, 30),
RST_PWR = _REG_BIT(0x38, 28),
RST_FDCAN = _REG_BIT(0x38, 25),
RST_USB = _REG_BIT(0x38, 23),
RST_I2C2 = _REG_BIT(0x38, 22),
RST_I2C1 = _REG_BIT(0x38, 21),
RST_UART5 = _REG_BIT(0x38, 20),
RST_UART4 = _REG_BIT(0x38, 19),
RST_USART3 = _REG_BIT(0x38, 18),
RST_USART2 = _REG_BIT(0x38, 17),
RST_SPI3 = _REG_BIT(0x38, 15),
RST_SPI2 = _REG_BIT(0x38, 14),
RST_CRS = _REG_BIT(0x38, 8),
RST_TIM7 = _REG_BIT(0x38, 5),
RST_TIM6 = _REG_BIT(0x38, 4),
RST_TIM5 = _REG_BIT(0x38, 3),
RST_TIM4 = _REG_BIT(0x38, 2),
RST_TIM3 = _REG_BIT(0x38, 1),
RST_TIM2 = _REG_BIT(0x38, 0),
RST_LPTIM1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 31),
RST_I2C3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 30),
RST_PWR = _REG_BIT(RCC_APB1RSTR1_OFFSET, 28),
RST_FDCAN = _REG_BIT(RCC_APB1RSTR1_OFFSET, 25),
RST_USB = _REG_BIT(RCC_APB1RSTR1_OFFSET, 23),
RST_I2C2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 22),
RST_I2C1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 21),
RST_UART5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 20),
RST_UART4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 19),
RST_USART3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 18),
RST_USART2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 17),
RST_SPI3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 15),
RST_SPI2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 14),
RST_CRS = _REG_BIT(RCC_APB1RSTR1_OFFSET, 8),
RST_TIM7 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 5),
RST_TIM6 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 4),
RST_TIM5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 3),
RST_TIM4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 2),
RST_TIM3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 1),
RST_TIM2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 0),
/* apb1-2 */
RST_UCPD1 = _REG_BIT(0x3c, 8),
RST_I2C4 = _REG_BIT(0x3c, 1),
RST_LPUART1 = _REG_BIT(0x3c, 0),
RST_UCPD1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 8),
RST_I2C4 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 1),
RST_LPUART1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 0),
/* APB2 peripherals */
RST_HRTIM1 = _REG_BIT(0x40, 26),
RST_SAI1 = _REG_BIT(0x40, 21),
RST_TIM20 = _REG_BIT(0x40, 20),
RST_TIM17 = _REG_BIT(0x40, 18),
RST_TIM16 = _REG_BIT(0x40, 17),
RST_TIM15 = _REG_BIT(0x40, 16),
RST_SPI4 = _REG_BIT(0x40, 15),
RST_USART1 = _REG_BIT(0x40, 14),
RST_TIM8 = _REG_BIT(0x40, 13),
RST_SPI1 = _REG_BIT(0x40, 12),
RST_TIM1 = _REG_BIT(0x40, 11),
RST_SYSCFG = _REG_BIT(0x40, 0),
RST_HRTIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 26),
RST_SAI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 21),
RST_TIM20 = _REG_BIT(RCC_APB2RSTR_OFFSET, 20),
RST_TIM17 = _REG_BIT(RCC_APB2RSTR_OFFSET, 18),
RST_TIM16 = _REG_BIT(RCC_APB2RSTR_OFFSET, 17),
RST_TIM15 = _REG_BIT(RCC_APB2RSTR_OFFSET, 16),
RST_SPI4 = _REG_BIT(RCC_APB2RSTR_OFFSET, 15),
RST_USART1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 14),
RST_TIM8 = _REG_BIT(RCC_APB2RSTR_OFFSET, 13),
RST_SPI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 12),
RST_TIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 11),
RST_SYSCFG = _REG_BIT(RCC_APB2RSTR_OFFSET, 0),
};
#undef _REG_BIT
#include <libopencm3/stm32/common/rcc_common_all.h>
BEGIN_DECLS
void rcc_osc_ready_int_clear(enum rcc_osc osc);
void rcc_osc_ready_int_enable(enum rcc_osc osc);
void rcc_osc_ready_int_disable(enum rcc_osc osc);
int rcc_osc_ready_int_flag(enum rcc_osc osc);
void rcc_css_int_clear(void);
int rcc_css_int_flag(void);
void rcc_wait_for_sysclk_status(enum rcc_osc osc);
void rcc_osc_on(enum rcc_osc osc);
void rcc_osc_off(enum rcc_osc osc);
void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_main_pll(uint32_t pllsrc, uint32_t pllm, uint32_t plln,
uint32_t pllp, uint32_t pllq, uint32_t pllr);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock);
void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement"))) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock);
void rcc_set_clock48_source(uint32_t clksel);
END_DECLS

2
lib/stm32/g4/Makefile
View File

@@ -38,7 +38,7 @@ ARFLAGS = rcs
OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o
OBJS += gpio_common_all.o gpio_common_f0234.o
OBJS += pwr.o
OBJS += rcc_common_all.o
OBJS += rcc.o rcc_common_all.o
VPATH += ../../usb:../:../../cm3:../common
VPATH += ../../ethernet

766
lib/stm32/g4/rcc.c Normal file
View File

@@ -0,0 +1,766 @@
/** @defgroup rcc_file RCC peripheral API
*
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32G4xx Reset and Clock Control</b>
*
* @author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
* @author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
* @author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran at seznam.cz>
* @author @htmlonly &copy; @endhtmlonly 2020 Sam Kirkham <sam.kirkham@codethink.co.uk>
* @author @htmlonly &copy; @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* @date 30 July 2020
*
* This library supports the Reset and Clock Control System in the STM32 series
* of ARM Cortex Microcontrollers by ST Microelectronics.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2013 Frantisek Burian <BuFran at seznam.cz>
* Copyright (C) 2020 Sam Kirkham <sam.kirkham@codethink.co.uk>
* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/flash.h>
/**@{*/
/* Set the default clock frequencies after reset. */
uint32_t rcc_ahb_frequency = 16000000;
uint32_t rcc_apb1_frequency = 16000000;
uint32_t rcc_apb2_frequency = 16000000;
const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 2,
.plln = 24,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 4,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 1,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 1,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 1,
.plln = 24,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 2,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 2,
.plln = 16,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 2,
.plln = 16,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 2,
.plln = 32,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 3,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 2,
.plln = 24,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 4,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
void rcc_osc_ready_int_clear(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CICR |= RCC_CICR_HSI48RDYC;
break;
case RCC_PLL:
RCC_CICR |= RCC_CICR_PLLRDYC;
break;
case RCC_HSE:
RCC_CICR |= RCC_CICR_HSERDYC;
break;
case RCC_HSI16:
RCC_CICR |= RCC_CICR_HSIRDYC;
break;
case RCC_LSE:
RCC_CICR |= RCC_CICR_LSERDYC;
break;
case RCC_LSI:
RCC_CICR |= RCC_CICR_LSIRDYC;
break;
}
}
void rcc_osc_ready_int_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CIER |= RCC_CIER_HSI48RDYIE;
break;
case RCC_PLL:
RCC_CIER |= RCC_CIER_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIER |= RCC_CIER_HSERDYIE;
break;
case RCC_HSI16:
RCC_CIER |= RCC_CIER_HSIRDYIE;
break;
case RCC_LSE:
RCC_CIER |= RCC_CIER_LSERDYIE;
break;
case RCC_LSI:
RCC_CIER |= RCC_CIER_LSIRDYIE;
break;
}
}
void rcc_osc_ready_int_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CIER &= ~RCC_CIER_HSI48RDYIE;
break;
case RCC_PLL:
RCC_CIER &= ~RCC_CIER_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIER &= ~RCC_CIER_HSERDYIE;
break;
case RCC_HSI16:
RCC_CIER &= ~RCC_CIER_HSIRDYIE;
break;
case RCC_LSE:
RCC_CIER &= ~RCC_CIER_LSERDYIE;
break;
case RCC_LSI:
RCC_CIER &= ~RCC_CIER_LSIRDYIE;
break;
}
}
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
return ((RCC_CIFR & RCC_CIFR_HSI48RDYF) != 0);
case RCC_PLL:
return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
case RCC_HSE:
return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
case RCC_HSI16:
return ((RCC_CIFR & RCC_CIFR_HSIRDYF) != 0);
case RCC_LSE:
return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
case RCC_LSI:
return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
}
return 0;
}
void rcc_css_int_clear(void)
{
RCC_CICR |= RCC_CICR_CSSC;
}
int rcc_css_int_flag(void)
{
return ((RCC_CIFR & RCC_CIFR_CSSF) != 0);
}
bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
return RCC_CRRCR & RCC_CRRCR_HSI48RDY;
case RCC_PLL:
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI16:
return RCC_CR & RCC_CR_HSIRDY;
case RCC_LSE:
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}
void rcc_wait_for_osc_ready(enum rcc_osc osc)
{
while (!rcc_is_osc_ready(osc));
}
void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWx_PLL);
break;
case RCC_HSE:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWx_HSE);
break;
case RCC_HSI16:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWx_HSI16);
break;
default:
/* Shouldn't be reached. */
break;
}
}
void rcc_osc_on(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CRRCR |= RCC_CRRCR_HSI48ON;
break;
case RCC_PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case RCC_HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case RCC_HSI16:
RCC_CR |= RCC_CR_HSION;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case RCC_LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
}
void rcc_osc_off(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CRRCR &= ~RCC_CRRCR_HSI48ON;
break;
case RCC_PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case RCC_HSI16:
RCC_CR &= ~RCC_CR_HSION;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case RCC_LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
}
void rcc_css_enable(void)
{
RCC_CR |= RCC_CR_CSSON;
}
void rcc_css_disable(void)
{
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_set_sysclk_source(uint32_t clk)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
RCC_CFGR = (reg32 | (clk << RCC_CFGR_SW_SHIFT));
}
void rcc_set_pll_source(uint32_t pllsrc)
{
uint32_t reg32;
reg32 = RCC_PLLCFGR;
reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT);
RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT));
}
void rcc_set_ppre2(uint32_t ppre2)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
}
void rcc_set_ppre1(uint32_t ppre1)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
}
void rcc_set_hpre(uint32_t hpre)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
}
/**
* Reconfigures the main PLL for a HSE source.
* Any reserved bits are kept at their reset values.
* @param pllsrc Source for the main PLL input clock
* @param pllm Divider for the main PLL input clock
* @param plln Main PLL multiplication factor for VCO
* @param pllp Main PLL divider for ADC
* @param pllq Main PLL divider for QUADSPI, FDCAN, USB, SAI & I2S
* @param pllr Main PLL divider for main system clock
*/
void rcc_set_main_pll(uint32_t pllsrc, uint32_t pllm, uint32_t plln,
uint32_t pllp, uint32_t pllq, uint32_t pllr)
{
bool pllpen = (pllp != 0);
bool pllqen = (pllq != 0);
bool pllren = (pllr != 0);
pllm -= 1;
uint32_t pllpdiv = pllp;
pllp = (pllpdiv == 17);
if ((pllpdiv == 7) || (pllpdiv == 17)) {
pllpdiv = 0;
}
pllr = (pllr >> 1) - 1;
pllq = (pllq >> 1) - 1;
RCC_PLLCFGR = ((pllsrc & RCC_PLLCFGR_PLLSRC_MASK) << RCC_PLLCFGR_PLLSRC_SHIFT) |
((pllm & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_SHIFT) |
((plln & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_SHIFT) |
(pllpen ? RCC_PLLCFGR_PLLPEN : 0 ) |
(pllp ? RCC_PLLCFGR_PLLP_DIV17 : RCC_PLLCFGR_PLLP_DIV7) |
(pllqen ? RCC_PLLCFGR_PLLQEN : 0 ) |
((pllq & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_SHIFT) |
(pllren ? RCC_PLLCFGR_PLLREN : 0 ) |
((pllr & RCC_PLLCFGR_PLLR_MASK) << RCC_PLLCFGR_PLLR_SHIFT) |
((pllpdiv & RCC_PLLCFGR_PLLPDIV_MASK) << RCC_PLLCFGR_PLLPDIV_SHIFT);
}
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
}
/**
* Setup clocks to run from PLL.
*
* The arguments provide the pll source, multipliers, dividers, all that's
* needed to establish a system clock.
*
* @param clock clock information structure.
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
/* Enable internal high-speed oscillator (HSI16). */
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
/* Select HSI16 as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SWx_HSI16);
/* Enable external high-speed oscillator (HSE). */
if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
}
/* Set the VOS scale mode */
rcc_periph_clock_enable(RCC_PWR);
pwr_set_vos_scale(clock->vos_scale);
if (clock->boost) {
pwr_enable_boost();
} else {
pwr_disable_boost();
}
/*
* Set prescalers for AHB, ADC, APB1, APB2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
/* Disable PLL oscillator before changing its configuration. */
rcc_osc_off(RCC_PLL);
/* Configure the PLL oscillator. */
rcc_set_main_pll(clock->pll_source,
clock->pllm, clock->plln,
clock->pllp, clock->pllq, clock->pllr);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
if (clock->flash_config & FLASH_ACR_DCEN) {
flash_dcache_enable();
} else {
flash_dcache_disable();
}
if (clock->flash_config & FLASH_ACR_ICEN) {
flash_icache_enable();
} else {
flash_icache_disable();
}
flash_set_ws(clock->flash_waitstates);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SWx_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
/* Disable internal high-speed oscillator. */
if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) {
rcc_osc_off(RCC_HSI16);
}
}
/**
* Setup clocks with the HSE.
*
* @deprecated replaced by rcc_clock_setup_pll as a drop in replacement.
* @see rcc_clock_setup_pll which supports HSI16 as well as HSE, using the same
* clock structures.
*/
void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
{
rcc_clock_setup_pll(clock);
}
/** Set clock source for 48MHz clock
*
* The 48 MHz clock is derived from one of the four following sources:
* - PLLQ VCO (RCC_CCIPR_CLK48_PLLQ)
* - HSI48 internal oscillator (RCC_CCIPR_CLK48_HSI48)
*
* @param clksel One of the definitions above
*/
void rcc_set_clock48_source(uint32_t clksel)
{
RCC_CCIPR &= ~(RCC_CCIPR_SEL_MASK << RCC_CCIPR_CLK48_SHIFT);
RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48_SHIFT);
}
/**@}*/