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stm32g4: rcc: use datasheet naming for CCIPR fields

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Follow HACKING specifications, be consistent with all other parts.
Yes, the SEL suffix is kinda superfluous, but it's _consistent_ which is
why we do it.

Signed-off-by: Karl Palsson <karlp@tweak.au>
This commit is contained in:
Karl Palsson
2023-02-02 23:35:51 +00:00
parent 66e2cc3ea8
commit f0575c3560
2 changed files with 55 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

105
include/libopencm3/stm32/g4/rcc.h
View File

@@ -572,69 +572,70 @@
/* all fields are 2 bits */
#define RCC_CCIPR_SEL_MASK 0x3
#define RCC_CCIPR_ADC345_NONE 0
#define RCC_CCIPR_ADC345_PLLP 1
#define RCC_CCIPR_ADC345_SYS 2
#define RCC_CCIPR_ADC345_SHIFT 30
#define RCC_CCIPR_ADC345SEL_NONE 0
#define RCC_CCIPR_ADC345SEL_PLLP 1
#define RCC_CCIPR_ADC345SEL_SYS 2
#define RCC_CCIPR_ADC345SEL_SHIFT 30
#define RCC_CCIPR_ADC12_NONE 0
#define RCC_CCIPR_ADC12_PLLP 1
#define RCC_CCIPR_ADC12_SYS 2
#define RCC_CCIPR_ADC12_SHIFT 28
#define RCC_CCIPR_ADC12SEL_NONE 0
#define RCC_CCIPR_ADC12SEL_PLLP 1
#define RCC_CCIPR_ADC12SEL_SYS 2
#define RCC_CCIPR_ADC12SEL_SHIFT 28
#define RCC_CCIPR_CLK48_HSI48 0
#define RCC_CCIPR_CLK48_PLLQ 2
#define RCC_CCIPR_CLK48_SHIFT 26
#define RCC_CCIPR_CLK48SEL_HSI48 0
#define RCC_CCIPR_CLK48SEL_PLLQ 2
#define RCC_CCIPR_CLK48SEL_SHIFT 26
#define RCC_CCIPR_FDCAN_HSE 0
#define RCC_CCIPR_FDCAN_PLLQ 1
#define RCC_CCIPR_FDCAN_PCLK 2
#define RCC_CCIPR_FDCAN_SHIFT 24
#define RCC_CCIPR_FDCANSEL_HSE 0
#define RCC_CCIPR_FDCANSEL_PLLQ 1
#define RCC_CCIPR_FDCANSEL_PCLK 2
#define RCC_CCIPR_FDCANSEL_SHIFT 24
#define RCC_CCIPR_I2S23_SYS 0
#define RCC_CCIPR_I2S23_PLLQ 1
#define RCC_CCIPR_I2S23_EXT 2
#define RCC_CCIPR_I2S23_SHI16 3
#define RCC_CCIPR_I2S23_SHIFT 22
#define RCC_CCIPR_I2S23SEL_SYS 0
#define RCC_CCIPR_I2S23SEL_PLLQ 1
#define RCC_CCIPR_I2S23SEL_EXT 2
#define RCC_CCIPR_I2S23SEL_SHI16 3
#define RCC_CCIPR_I2S23SEL_SHIFT 22
#define RCC_CCIPR_SAI1_SYS 0
#define RCC_CCIPR_SAI1_PLLQ 1
#define RCC_CCIPR_SAI1_EXT 2
#define RCC_CCIPR_SAI1_HSI16 3
#define RCC_CCIPR_SAI1_SHIFT 20
#define RCC_CCIPR_SAI1SEL_SYS 0
#define RCC_CCIPR_SAI1SEL_PLLQ 1
#define RCC_CCIPR_SAI1SEL_EXT 2
#define RCC_CCIPR_SAI1SEL_HSI16 3
#define RCC_CCIPR_SAI1SEL_SHIFT 20
#define RCC_CCIPR_LPTIM1_PCLK 0
#define RCC_CCIPR_LPTIM1_LSI 1
#define RCC_CCIPR_LPTIM1_HSI16 2
#define RCC_CCIPR_LPTIM1_LSE 3
#define RCC_CCIPR_LPTIM1SEL_PCLK 0
#define RCC_CCIPR_LPTIM1SEL_LSI 1
#define RCC_CCIPR_LPTIM1SEL_HSI16 2
#define RCC_CCIPR_LPTIM1SEL_LSE 3
#define RCC_CCIPR_LPTIM1SEL_SHIFT 18
#define RCC_CCIPR_I2Cx_PCLK 0
#define RCC_CCIPR_I2Cx_SYS 1
#define RCC_CCIPR_I2Cx_HSI16 2
#define RCC_CCIPR_I2C3_SHIFT 16
#define RCC_CCIPR_I2C2_SHIFT 14
#define RCC_CCIPR_I2C1_SHIFT 12
#define RCC_CCIPR_I2CxSEL_PCLK 0
#define RCC_CCIPR_I2CxSEL_SYS 1
#define RCC_CCIPR_I2CxSEL_HSI16 2
#define RCC_CCIPR_I2C3SEL_SHIFT 16
#define RCC_CCIPR_I2C2SEL_SHIFT 14
#define RCC_CCIPR_I2C1SEL_SHIFT 12
#define RCC_CCIPR_LPUART1_PCLK 0
#define RCC_CCIPR_LPUART1_SYS 1
#define RCC_CCIPR_LPUART1_HSI16 2
#define RCC_CCIPR_LPUART1_LSE 3
#define RCC_CCIPR_USARTxSEL_PCLK 0
#define RCC_CCIPR_USARTxSEL_SYSCLK 1
#define RCC_CCIPR_USARTxSEL_HSI16 2
#define RCC_CCIPR_USARTxSEL_LSE 3
#define RCC_CCIPR_LPUARTxSEL_PCLK RCC_CCIPR_USARTx_PCLK
#define RCC_CCIPR_LPUARTxSEL_SYSCLK RCC_CCIPR_USARTx_SYSCLK
#define RCC_CCIPR_LPUARTxSEL_HSI16 RCC_CCIPR_USARTx_HSI16
#define RCC_CCIPR_LPUARTxSEL_LSE RCC_CCIPR_USARTx_LSE
#define RCC_CCIPR_LPUART1SEL_SHIFT 10
#define RCC_CCIPR_USARTx_PCLK 0
#define RCC_CCIPR_USARTx_SYS 1
#define RCC_CCIPR_USARTx_HSI16 2
#define RCC_CCIPR_USARTx_LSE 3
#define RCC_CCIPR_UARTx_PCLK RCC_CCIPR_USARTx_PCLK
#define RCC_CCIPR_UARTx_SYS RCC_CCIPR_USARTx_SYS
#define RCC_CCIPR_UARTx_HSI16 RCC_CCIPR_USARTx_HSI16
#define RCC_CCIPR_UARTx_LSE RCC_CCIPR_USARTx_LSE
#define RCC_CCIPR_UART5_SHIFT 8
#define RCC_CCIPR_UART4_SHIFT 6
#define RCC_CCIPR_USART3_SHIFT 4
#define RCC_CCIPR_USART2_SHIFT 2
#define RCC_CCIPR_USART1_SHIFT 0
#define RCC_CCIPR_UARTxSEL_PCLK RCC_CCIPR_USARTx_PCLK
#define RCC_CCIPR_UARTxSEL_SYSCLK RCC_CCIPR_USARTx_SYSCLK
#define RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTx_HSI16
#define RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTx_LSE
#define RCC_CCIPR_UART5SEL_SHIFT 8
#define RCC_CCIPR_UART4SEL_SHIFT 6
#define RCC_CCIPR_USART3SEL_SHIFT 4
#define RCC_CCIPR_USART2SEL_SHIFT 2
#define RCC_CCIPR_USART1SEL_SHIFT 0
/**@}*/
/** defgroup rcc_ccipr2_values RCC_CCIPR2 - Peripherals independent clock config register 2

4
lib/stm32/g4/rcc.c
View File

@@ -759,8 +759,8 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
*/
void rcc_set_clock48_source(uint32_t clksel)
{
RCC_CCIPR &= ~(RCC_CCIPR_SEL_MASK << RCC_CCIPR_CLK48_SHIFT);
RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48_SHIFT);
RCC_CCIPR &= ~(RCC_CCIPR_SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT);
RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT);
}
/**@}*/