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BuFran
2013-07-11 13:54:22 +02:00
committed by Piotr Esden-Tempski
parent 210a17ec97
commit efc2489d2c
7 changed files with 39 additions and 37 deletions
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3
include/libopencm3/cm3/scs.h
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@@ -250,7 +250,8 @@
/* /*
* System Control Space (SCS) => Data Watchpoint and Trace (DWT). * System Control Space (SCS) => Data Watchpoint and Trace (DWT).
* See "ARMv7-M Architecture Reference Manual" * See "ARMv7-M Architecture Reference Manual"
* (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/ARMv7-M_ARM.pdf) * (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/
* ARMv7-M_ARM.pdf)
* The DWT is an optional debug unit that provides watchpoints, data tracing, * The DWT is an optional debug unit that provides watchpoints, data tracing,
* and system profiling for the processor. * and system profiling for the processor.
*/ */

7
include/libopencm3/stm32/common/syscfg_common_l1f234.h
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@@ -38,7 +38,7 @@ specific memorymap.h header before including this header file.*/
#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) #define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04)
/* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */ /* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */
#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) #define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4)
#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) #define SYSCFG_EXTICR1 SYSCFG_EXTICR(0)
#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) #define SYSCFG_EXTICR2 SYSCFG_EXTICR(1)
#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) #define SYSCFG_EXTICR3 SYSCFG_EXTICR(2)
@@ -50,6 +50,7 @@ specific memorymap.h header before including this header file.*/
/** @cond */ /** @cond */
#else #else
#warning "syscfg_common_l1f234.h should not be included explicitly, only via syscfg.h" #warning "syscfg_common_l1f234.h should not be included explicitly,"
#warning "only via syscfg.h"
#endif #endif
/** @endcond */ /** @endcond */

50
include/libopencm3/stm32/f0/tsc.h
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@@ -84,41 +84,41 @@
/* TSC_IOHCR Values --------------------------------------------------------*/ /* TSC_IOHCR Values --------------------------------------------------------*/
/* Bit helper g = [1..6] io = [1..4] */ /* Bit helper g = [1..6] io = [1..4] */
#define TSC_IOBIT_VAL(g,io) ((1 << ((io)-1)) << (((g)-1)*4)) #define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4))
#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1,io) #define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2,io) #define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3,io) #define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4,io) #define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5,io) #define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6,io) #define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOASCR Values -------------------------------------------------------*/ /* TSC_IOASCR Values -------------------------------------------------------*/
#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1,io) #define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2,io) #define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3,io) #define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4,io) #define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5,io) #define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6,io) #define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOSCR Values --------------------------------------------------------*/ /* TSC_IOSCR Values --------------------------------------------------------*/
#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1,io) #define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2,io) #define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3,io) #define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4,io) #define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5,io) #define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6,io) #define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOCCR Values -------------------------------------------------------*/ /* TSC_IOCCR Values -------------------------------------------------------*/
#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1,io) #define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2,io) #define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3,io) #define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4,io) #define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5,io) #define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6,io) #define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOGCSR Values -------------------------------------------------------*/ /* TSC_IOGCSR Values -------------------------------------------------------*/

2
include/libopencm3/stm32/otg_fs.h
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@@ -89,7 +89,7 @@
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) #define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
/* Data FIFO */ /* Data FIFO */
#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \ #define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \
+ (((x) + 1) \ + (((x) + 1) \
<< 12))) << 12)))

4
lib/cm3/nvic.c
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@@ -138,9 +138,9 @@ uint8_t nvic_get_irq_enabled(uint8_t irqn)
* interpreted according to the pre-emptive priority grouping set in the * interpreted according to the pre-emptive priority grouping set in the
* SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done * SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done
* in @ref scb_set_priority_grouping. * in @ref scb_set_priority_grouping.
* *
* CM0: * CM0:
* *
* There are 4 priority levels only, given by the upper two bits of the * There are 4 priority levels only, given by the upper two bits of the
* priority byte, as required by ARM standards. No grouping available. * priority byte, as required by ARM standards. No grouping available.
* *

2
lib/cm3/sync.c
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@@ -65,7 +65,7 @@ void mutex_lock(mutex_t *m)
void mutex_unlock(mutex_t *m) void mutex_unlock(mutex_t *m)
{ {
/* Ensure accesses to protected resource are finished */ /* Ensure accesses to protected resource are finished */
__dmb(); __dmb();
/* Free the lock. */ /* Free the lock. */

8
lib/stm32/common/exti_common_all.c
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@@ -90,12 +90,12 @@ uint32_t exti_get_flag_status(uint32_t exti)
void exti_select_source(uint32_t exti, uint32_t gpioport) void exti_select_source(uint32_t exti, uint32_t gpioport)
{ {
uint32_t line; uint32_t line;
for (line=0; line<16; line++) for (line = 0; line < 16; line++) {
{ if (!(exti & (1 << line))) {
if (!(exti & (1 << line)))
continue; continue;
}
uint32_t bits = 0, mask=0x0F; uint32_t bits = 0, mask = 0x0F;
switch (gpioport) { switch (gpioport) {
case GPIOA: case GPIOA: