From efc2489d2cbb86177ba56e78a0487981408d1436 Mon Sep 17 00:00:00 2001 From: BuFran Date: Thu, 11 Jul 2013 13:54:22 +0200 Subject: [PATCH] [Stylecheck] Code cleaned to current stylecheck script --- include/libopencm3/cm3/scs.h | 3 +- .../stm32/common/syscfg_common_l1f234.h | 7 +-- include/libopencm3/stm32/f0/tsc.h | 50 +++++++++---------- include/libopencm3/stm32/otg_fs.h | 2 +- lib/cm3/nvic.c | 4 +- lib/cm3/sync.c | 2 +- lib/stm32/common/exti_common_all.c | 8 +-- 7 files changed, 39 insertions(+), 37 deletions(-) diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h index 9b7c0398..c0787170 100644 --- a/include/libopencm3/cm3/scs.h +++ b/include/libopencm3/cm3/scs.h @@ -250,7 +250,8 @@ /* * System Control Space (SCS) => Data Watchpoint and Trace (DWT). * See "ARMv7-M Architecture Reference Manual" - * (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/ARMv7-M_ARM.pdf) + * (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/ + * ARMv7-M_ARM.pdf) * The DWT is an optional debug unit that provides watchpoints, data tracing, * and system profiling for the processor. */ diff --git a/include/libopencm3/stm32/common/syscfg_common_l1f234.h b/include/libopencm3/stm32/common/syscfg_common_l1f234.h index 4684b286..e96dc399 100644 --- a/include/libopencm3/stm32/common/syscfg_common_l1f234.h +++ b/include/libopencm3/stm32/common/syscfg_common_l1f234.h @@ -38,7 +38,7 @@ specific memorymap.h header before including this header file.*/ #define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) /* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */ -#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) +#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) #define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) #define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) #define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) @@ -50,6 +50,7 @@ specific memorymap.h header before including this header file.*/ /** @cond */ #else -#warning "syscfg_common_l1f234.h should not be included explicitly, only via syscfg.h" +#warning "syscfg_common_l1f234.h should not be included explicitly," +#warning "only via syscfg.h" #endif -/** @endcond */ +/** @endcond */ diff --git a/include/libopencm3/stm32/f0/tsc.h b/include/libopencm3/stm32/f0/tsc.h index 0cca2f40..419ac778 100644 --- a/include/libopencm3/stm32/f0/tsc.h +++ b/include/libopencm3/stm32/f0/tsc.h @@ -84,41 +84,41 @@ /* TSC_IOHCR Values --------------------------------------------------------*/ /* Bit helper g = [1..6] io = [1..4] */ -#define TSC_IOBIT_VAL(g,io) ((1 << ((io)-1)) << (((g)-1)*4)) +#define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4)) -#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1,io) -#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2,io) -#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3,io) -#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4,io) -#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5,io) -#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6,io) +#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOASCR Values -------------------------------------------------------*/ -#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1,io) -#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2,io) -#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3,io) -#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4,io) -#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5,io) -#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6,io) +#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOSCR Values --------------------------------------------------------*/ -#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1,io) -#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2,io) -#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3,io) -#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4,io) -#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5,io) -#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6,io) +#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOCCR Values -------------------------------------------------------*/ -#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1,io) -#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2,io) -#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3,io) -#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4,io) -#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5,io) -#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6,io) +#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOGCSR Values -------------------------------------------------------*/ diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h index 1fb80acf..fc725987 100644 --- a/include/libopencm3/stm32/otg_fs.h +++ b/include/libopencm3/stm32/otg_fs.h @@ -89,7 +89,7 @@ #define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) /* Data FIFO */ -#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \ +#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \ + (((x) + 1) \ << 12))) diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c index 1a8f563a..e40e7872 100644 --- a/lib/cm3/nvic.c +++ b/lib/cm3/nvic.c @@ -138,9 +138,9 @@ uint8_t nvic_get_irq_enabled(uint8_t irqn) * interpreted according to the pre-emptive priority grouping set in the * SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done * in @ref scb_set_priority_grouping. - * + * * CM0: - * + * * There are 4 priority levels only, given by the upper two bits of the * priority byte, as required by ARM standards. No grouping available. * diff --git a/lib/cm3/sync.c b/lib/cm3/sync.c index 7ddd24db..3ab9b7e8 100644 --- a/lib/cm3/sync.c +++ b/lib/cm3/sync.c @@ -65,7 +65,7 @@ void mutex_lock(mutex_t *m) void mutex_unlock(mutex_t *m) { - /* Ensure accesses to protected resource are finished */ + /* Ensure accesses to protected resource are finished */ __dmb(); /* Free the lock. */ diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c index d64b80b1..aede62a2 100644 --- a/lib/stm32/common/exti_common_all.c +++ b/lib/stm32/common/exti_common_all.c @@ -90,12 +90,12 @@ uint32_t exti_get_flag_status(uint32_t exti) void exti_select_source(uint32_t exti, uint32_t gpioport) { uint32_t line; - for (line=0; line<16; line++) - { - if (!(exti & (1 << line))) + for (line = 0; line < 16; line++) { + if (!(exti & (1 << line))) { continue; + } - uint32_t bits = 0, mask=0x0F; + uint32_t bits = 0, mask = 0x0F; switch (gpioport) { case GPIOA: