Added I2C stm32u5_support

Tested I2C master mode on 16MHz HSI

include/libopencm3/stm32/i2c.h

@@ -38,6 +38,8 @@
 #       include <libopencm3/stm32/l1/i2c.h>
 #elif defined(STM32L4)
 #       include <libopencm3/stm32/l4/i2c.h>
+#elif defined(STM32U5)
+#       include <libopencm3/stm32/u5/i2c.h>
 #elif defined(STM32G0)
 #       include <libopencm3/stm32/g0/i2c.h>
 #elif defined(STM32G4)

include/libopencm3/stm32/u5/i2c.h

@@ -0,0 +1,38 @@
+/** @defgroup i2c_defines I2C Defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32U5xx I2C</b>
+ *
+ * @ingroup STM32U5xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date 13 Oct 2024
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/common/i2c_common_v2.h>
+
+#endif
+

include/libopencm3/stm32/u5/memorymap.h

@@ -191,7 +191,7 @@
 /* PERIPH_BASE_APB3 + 0x0400 (0x4600 0800 - 0x4600 1FFF): Reserved */
 #define SPI3_BASE			(PERIPH_BASE_APB3 + 0x1C00U)
 #define LPUART1_BASE		PERIPH_BASE_APB3 + 0x2000U)
-#define I2C3a_BASE			(PERIPH_BASE_APB3 + 0x2400U)
+#define I2C3_BASE			(PERIPH_BASE_APB3 + 0x2400U)
 /* PERIPH_BASE_APB3 + 0x2800 (0x4600 2C00 - 0x4600 43FF): Reserved */
 #define LPTIM1_BASE			(PERIPH_BASE_APB3 + 0x4000U)
 #define LPTIM3_BASE			(PERIPH_BASE_APB3 + 0x4400U)

include/libopencm3/stm32/u5/rcc.h

@@ -65,6 +65,7 @@ extern const struct rcc_clock_scale rcc_hsi16mhz_configs;
 #define RCC_CFGR3	MMIO32(RCC_BASE + 0x24)
 #define RCC_CCIPR1  MMIO32(RCC_BASE + 0xE0)
 #define RCC_CCIPR2  MMIO32(RCC_BASE + 0xE4)
+#define RCC_CCIPR3  MMIO32(RCC_BASE + 0xE8)
 
 
 
@@ -161,9 +162,20 @@ extern const struct rcc_clock_scale rcc_hsi16mhz_configs;
 #define RCC_BDCR			MMIO32(RCC_BASE + 0xF0)
 #define RCC_BDCR_LSEBYP		(1 << 2)
 
-/* --- RCC_CCIPR1 values ---------------------------------------------------- */
-
 #define RCC_CCIPR_USARTxSEL_MASK	0x3
+#define RCC_CCIPR_I2CxSEL_MASK		0x3
+
+#define RCC_CCIPR_USARTxSEL_PCLKx	0x0
+#define RCC_CCIPR_USARTxSEL_SYSCLK	0x1
+#define RCC_CCIPR_USARTxSEL_HSI16	0x2
+#define RCC_CCIPR_USARTxSEL_LSE		0x3
+
+#define RCC_CCIPR_I2CxSEL_PCLKx		0x0
+#define RCC_CCIPR_I2CxSEL_SYSCLK	0x1
+#define RCC_CCIPR_I2CxSEL_HSI16		0x2
+#define RCC_CCIPR_I2CxSEL_LSE		0x3
+
+/* --- RCC_CCIPR1 values ---------------------------------------------------- */
 
 #define RCC_CCIPR1_USART5SEL_SHIFT	8
 #define RCC_CCIPR1_USART4SEL_SHIFT	6
@@ -171,15 +183,20 @@ extern const struct rcc_clock_scale rcc_hsi16mhz_configs;
 #define RCC_CCIPR1_USART2SEL_SHIFT	2
 #define RCC_CCIPR1_USART1SEL_SHIFT	0
 
-#define RCC_CCIPR_USARTxSEL_PCLKx	0x0
+#define RCC_CCIPR1_I2C4SEL_SHIFT	14
-#define RCC_CCIPR_USARTxSEL_SYSCLK	0x1
+#define RCC_CCIPR1_I2C2SEL_SHIFT	12
-#define RCC_CCIPR_USARTxSEL_HSI16	0x2
+#define RCC_CCIPR1_I2C1SEL_SHIFT	10
-#define RCC_CCIPR_USARTxSEL_LSE		0x3
 
 /* --- RCC_CCIPR2 values ---------------------------------------------------- */
 
+#define RCC_CCIPR2_I2C6SEL_SHIFT	26
+#define RCC_CCIPR2_I2C5SEL_SHIFT	24
+
 #define RCC_CCIPR2_USART6SEL_SHIFT	16
 
+/* --- RCC_CCIPR3 values ---------------------------------------------------- */
+
+#define RCC_CCIPR3_I2C3SEL_SHIFT	6
 /*****************************************************************************/
 /* API definitions                                                           */
 /*****************************************************************************/

lib/stm32/u5/Makefile

@@ -35,6 +35,7 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 
 ARFLAGS		= rcs
 
+OBJS += i2c_common_v2.o
 OBJS += usart_common_all.o usart_common_v2.o
 OBJS += gpio_common_all.o gpio_common_f0234.o
 OBJS += rcc.o rcc_common_all.o

lib/stm32/u5/i2c.c

@@ -0,0 +1,31 @@
+/** @defgroup i2c_file I2C
+ *
+ * @ingroup STM32U5xx
+ *
+ * @brief <b>libopencm3 STM32U5xx I2C</b>
+ *
+ * @version 1.0.0
+ *
+ * @date 13 OCt 2024
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/i2c.h>

lib/stm32/u5/rcc.c

@@ -358,6 +358,36 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) {
 		shift = RCC_CCIPR2_USART6SEL_SHIFT;
 		mask = RCC_CCIPR_USARTxSEL_MASK;
 		break;
+	case I2C1_BASE:
+		reg32 = &RCC_CCIPR1;
+		shift = RCC_CCIPR1_I2C1SEL_SHIFT;
+		mask = RCC_CCIPR_I2CxSEL_MASK;
+		break;
+	case I2C2_BASE:
+		reg32 = &RCC_CCIPR1;
+		shift = RCC_CCIPR1_I2C2SEL_SHIFT;
+		mask = RCC_CCIPR_I2CxSEL_MASK;
+		break;
+	case I2C3_BASE:
+		reg32 = &RCC_CCIPR3;
+		shift = RCC_CCIPR3_I2C3SEL_SHIFT;
+		mask = RCC_CCIPR_I2CxSEL_MASK;
+		break;
+	case I2C4_BASE:
+		reg32 = &RCC_CCIPR1;
+		shift = RCC_CCIPR1_I2C4SEL_SHIFT;
+		mask = RCC_CCIPR_I2CxSEL_MASK;
+		break;
+	case I2C5_BASE:
+		reg32 = &RCC_CCIPR2;
+		shift = RCC_CCIPR2_I2C5SEL_SHIFT;
+		mask = RCC_CCIPR_I2CxSEL_MASK;
+		break;
+	case I2C6_BASE:
+		reg32 = &RCC_CCIPR2;
+		shift = RCC_CCIPR2_I2C6SEL_SHIFT;
+		mask = RCC_CCIPR_I2CxSEL_MASK;
+		break;
 	default:
 		cm3_assert_not_reached();
 		break;