diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h index 90b19889..eab9eee3 100644 --- a/include/libopencm3/stm32/i2c.h +++ b/include/libopencm3/stm32/i2c.h @@ -38,6 +38,8 @@ # include #elif defined(STM32L4) # include +#elif defined(STM32U5) +# include #elif defined(STM32G0) # include #elif defined(STM32G4) diff --git a/include/libopencm3/stm32/u5/i2c.h b/include/libopencm3/stm32/u5/i2c.h new file mode 100644 index 00000000..90811be2 --- /dev/null +++ b/include/libopencm3/stm32/u5/i2c.h @@ -0,0 +1,38 @@ +/** @defgroup i2c_defines I2C Defines + * + * @brief Defined Constants and Types for the STM32U5xx I2C + * + * @ingroup STM32U5xx_defines + * + * @version 1.0.0 + * + * @date 13 Oct 2024 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include + +#endif + diff --git a/include/libopencm3/stm32/u5/memorymap.h b/include/libopencm3/stm32/u5/memorymap.h index 2c5523fe..c5289ba4 100644 --- a/include/libopencm3/stm32/u5/memorymap.h +++ b/include/libopencm3/stm32/u5/memorymap.h @@ -191,7 +191,7 @@ /* PERIPH_BASE_APB3 + 0x0400 (0x4600 0800 - 0x4600 1FFF): Reserved */ #define SPI3_BASE (PERIPH_BASE_APB3 + 0x1C00U) #define LPUART1_BASE PERIPH_BASE_APB3 + 0x2000U) -#define I2C3a_BASE (PERIPH_BASE_APB3 + 0x2400U) +#define I2C3_BASE (PERIPH_BASE_APB3 + 0x2400U) /* PERIPH_BASE_APB3 + 0x2800 (0x4600 2C00 - 0x4600 43FF): Reserved */ #define LPTIM1_BASE (PERIPH_BASE_APB3 + 0x4000U) #define LPTIM3_BASE (PERIPH_BASE_APB3 + 0x4400U) diff --git a/include/libopencm3/stm32/u5/rcc.h b/include/libopencm3/stm32/u5/rcc.h index f109ccc5..b75f08e8 100644 --- a/include/libopencm3/stm32/u5/rcc.h +++ b/include/libopencm3/stm32/u5/rcc.h @@ -65,6 +65,7 @@ extern const struct rcc_clock_scale rcc_hsi16mhz_configs; #define RCC_CFGR3 MMIO32(RCC_BASE + 0x24) #define RCC_CCIPR1 MMIO32(RCC_BASE + 0xE0) #define RCC_CCIPR2 MMIO32(RCC_BASE + 0xE4) +#define RCC_CCIPR3 MMIO32(RCC_BASE + 0xE8) @@ -161,9 +162,20 @@ extern const struct rcc_clock_scale rcc_hsi16mhz_configs; #define RCC_BDCR MMIO32(RCC_BASE + 0xF0) #define RCC_BDCR_LSEBYP (1 << 2) -/* --- RCC_CCIPR1 values ---------------------------------------------------- */ - #define RCC_CCIPR_USARTxSEL_MASK 0x3 +#define RCC_CCIPR_I2CxSEL_MASK 0x3 + +#define RCC_CCIPR_USARTxSEL_PCLKx 0x0 +#define RCC_CCIPR_USARTxSEL_SYSCLK 0x1 +#define RCC_CCIPR_USARTxSEL_HSI16 0x2 +#define RCC_CCIPR_USARTxSEL_LSE 0x3 + +#define RCC_CCIPR_I2CxSEL_PCLKx 0x0 +#define RCC_CCIPR_I2CxSEL_SYSCLK 0x1 +#define RCC_CCIPR_I2CxSEL_HSI16 0x2 +#define RCC_CCIPR_I2CxSEL_LSE 0x3 + +/* --- RCC_CCIPR1 values ---------------------------------------------------- */ #define RCC_CCIPR1_USART5SEL_SHIFT 8 #define RCC_CCIPR1_USART4SEL_SHIFT 6 @@ -171,15 +183,20 @@ extern const struct rcc_clock_scale rcc_hsi16mhz_configs; #define RCC_CCIPR1_USART2SEL_SHIFT 2 #define RCC_CCIPR1_USART1SEL_SHIFT 0 -#define RCC_CCIPR_USARTxSEL_PCLKx 0x0 -#define RCC_CCIPR_USARTxSEL_SYSCLK 0x1 -#define RCC_CCIPR_USARTxSEL_HSI16 0x2 -#define RCC_CCIPR_USARTxSEL_LSE 0x3 +#define RCC_CCIPR1_I2C4SEL_SHIFT 14 +#define RCC_CCIPR1_I2C2SEL_SHIFT 12 +#define RCC_CCIPR1_I2C1SEL_SHIFT 10 /* --- RCC_CCIPR2 values ---------------------------------------------------- */ +#define RCC_CCIPR2_I2C6SEL_SHIFT 26 +#define RCC_CCIPR2_I2C5SEL_SHIFT 24 + #define RCC_CCIPR2_USART6SEL_SHIFT 16 +/* --- RCC_CCIPR3 values ---------------------------------------------------- */ + +#define RCC_CCIPR3_I2C3SEL_SHIFT 6 /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ diff --git a/lib/stm32/u5/Makefile b/lib/stm32/u5/Makefile index 537402f1..f61d35df 100644 --- a/lib/stm32/u5/Makefile +++ b/lib/stm32/u5/Makefile @@ -35,6 +35,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs +OBJS += i2c_common_v2.o OBJS += usart_common_all.o usart_common_v2.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += rcc.o rcc_common_all.o diff --git a/lib/stm32/u5/i2c.c b/lib/stm32/u5/i2c.c new file mode 100644 index 00000000..87aecdac --- /dev/null +++ b/lib/stm32/u5/i2c.c @@ -0,0 +1,31 @@ +/** @defgroup i2c_file I2C + * + * @ingroup STM32U5xx + * + * @brief libopencm3 STM32U5xx I2C + * + * @version 1.0.0 + * + * @date 13 OCt 2024 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include \ No newline at end of file diff --git a/lib/stm32/u5/rcc.c b/lib/stm32/u5/rcc.c index 7f0d9fd9..dd74c20c 100644 --- a/lib/stm32/u5/rcc.c +++ b/lib/stm32/u5/rcc.c @@ -358,6 +358,36 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) { shift = RCC_CCIPR2_USART6SEL_SHIFT; mask = RCC_CCIPR_USARTxSEL_MASK; break; + case I2C1_BASE: + reg32 = &RCC_CCIPR1; + shift = RCC_CCIPR1_I2C1SEL_SHIFT; + mask = RCC_CCIPR_I2CxSEL_MASK; + break; + case I2C2_BASE: + reg32 = &RCC_CCIPR1; + shift = RCC_CCIPR1_I2C2SEL_SHIFT; + mask = RCC_CCIPR_I2CxSEL_MASK; + break; + case I2C3_BASE: + reg32 = &RCC_CCIPR3; + shift = RCC_CCIPR3_I2C3SEL_SHIFT; + mask = RCC_CCIPR_I2CxSEL_MASK; + break; + case I2C4_BASE: + reg32 = &RCC_CCIPR1; + shift = RCC_CCIPR1_I2C4SEL_SHIFT; + mask = RCC_CCIPR_I2CxSEL_MASK; + break; + case I2C5_BASE: + reg32 = &RCC_CCIPR2; + shift = RCC_CCIPR2_I2C5SEL_SHIFT; + mask = RCC_CCIPR_I2CxSEL_MASK; + break; + case I2C6_BASE: + reg32 = &RCC_CCIPR2; + shift = RCC_CCIPR2_I2C6SEL_SHIFT; + mask = RCC_CCIPR_I2CxSEL_MASK; + break; default: cm3_assert_not_reached(); break;