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stm32g0: add base, irqs, memorymap and current devices.

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This commit is contained in:
Guillaume Revaillot
2019-01-23 19:00:51 +01:00
committed by Karl Palsson
parent 8a952d8476
commit b8d4b03722
9 changed files with 192 additions and 1 deletions
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2
include/libopencm3/dispatch/nvic.h
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@@ -20,6 +20,8 @@
# include <libopencm3/stm32/l1/nvic.h>
#elif defined(STM32L4)
# include <libopencm3/stm32/l4/nvic.h>
#elif defined(STM32G0)
# include <libopencm3/stm32/g0/nvic.h>
#elif defined(GD32F1X0)
# include <libopencm3/gd32/f1x0/nvic.h>

39
include/libopencm3/stm32/g0/irq.json Normal file
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@@ -0,0 +1,39 @@
{
"irqs": [
"wwdg",
"pvd",
"rtc",
"flash",
"rcc",
"exti0_1",
"exti2_3",
"exti4_15",
"ucpd1_ucpd2",
"dma1_channel1",
"dma1_channel2_3",
"dma1_channel4_7_dmamux",
"adc_comp",
"tim1_brk_up_trg_com",
"tim1_cc",
"tim2",
"tim3",
"tim6_dac_lptim1",
"tim7_lptim2",
"tim14",
"tim15",
"tim16",
"tim17",
"i2c1",
"i2c2",
"spi1",
"spi2",
"usart1",
"usart2",
"usart3_usart4_lpuart1",
"cec",
"aes_rng"
],
"partname_humanreadable": "STM32 G0 series",
"partname_doxygen": "STM32G0",
"includeguard": "LIBOPENCM3_STM32_G0_NVIC_H"
}

91
include/libopencm3/stm32/g0/memorymap.h Normal file
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@@ -0,0 +1,91 @@
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_MEMORYMAP_H
#define LIBOPENCM3_MEMORYMAP_H
#include <libopencm3/cm3/memorymap.h>
#define PERIPH_BASE (0x40000000U)
#define IOPORT_BASE (0x50000000U)
#define INFO_BASE (0x1fff7500U)
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
/* APB1 */
#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
#define USART4_BASE (PERIPH_BASE_APB1 + 0x4C00)
#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800)
#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)
#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)
#define LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)
#define UCPD1_BASE (PERIPH_BASE_APB1 + 0xA000)
#define UCPD2_BASE (PERIPH_BASE_APB1 + 0xA400)
#define TAMP_BASE (PERIPH_BASE_APB1 + 0xB000)
/* APB2 */
#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
#define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)
#define SYSCFG_ITLINE_BASE (PERIPH_BASE_APB2 + 0x0080)
#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200)
#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
#define TIM1_BASE (PERIPH_BASE_APB1 + 0x2C00)
#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
#define TIM15_BASE (PERIPH_BASE_APB1 + 0x4000)
#define TIM16_BASE (PERIPH_BASE_APB1 + 0x4400)
#define TIM17_BASE (PERIPH_BASE_APB1 + 0x4800)
#define DBGMCU_BASE (PERIPH_BASE_APB2 + 0x5800)
/* AHB */
#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000)
#define DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)
#define RCC_BASE (PERIPH_BASE_AHB + 0x01000)
#define EXTI_BASE (PERIPH_BASE_AHB + 0x01800)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
#define RNG_BASE (PERIPH_BASE_AHB + 0x05000)
#define AES_BASE (PERIPH_BASE_AHB + 0x06000)
#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)
#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)
#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)
#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)
#define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)
#define GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)
/* ST provided factory calibration values @ 3.0V */
#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))
#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))
#define ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))
#endif

2
include/libopencm3/stm32/memorymap.h
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@@ -38,6 +38,8 @@
# include <libopencm3/stm32/l1/memorymap.h>
#elif defined(STM32L4)
# include <libopencm3/stm32/l4/memorymap.h>
#elif defined(STM32G0)
# include <libopencm3/stm32/g0/memorymap.h>
#elif defined(GD32F1X0)
# include <libopencm3/gd32/f1x0/memorymap.h>
#else

2
include/libopencmsis/dispatch/irqhandlers.h
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@@ -16,6 +16,8 @@
# include <libopencmsis/stm32/l1/irqhandlers.h>
#elif defined(STM32L4)
# include <libopencmsis/stm32/l4/irqhandlers.h>
#elif defined(STM32G0)
# include <libopencmsis/stm32/l4/irqhandlers.h>
#elif defined(GD32F1X0)
# include <libopencmsis/gd32/f1x0/irqhandlers.h>