From b8d4b037229b9f3faecd905f3ef16d3fa849ce74 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 23 Jan 2019 19:00:51 +0100 Subject: [PATCH] stm32g0: add base, irqs, memorymap and current devices. --- Makefile | 1 + include/libopencm3/dispatch/nvic.h | 2 + include/libopencm3/stm32/g0/irq.json | 39 +++++++++ include/libopencm3/stm32/g0/memorymap.h | 91 +++++++++++++++++++++ include/libopencm3/stm32/memorymap.h | 2 + include/libopencmsis/dispatch/irqhandlers.h | 2 + ld/devices.data | 10 ++- lib/dispatch/vector_nvic.c | 2 + lib/stm32/g0/Makefile | 44 ++++++++++ 9 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 include/libopencm3/stm32/g0/irq.json create mode 100644 include/libopencm3/stm32/g0/memorymap.h create mode 100644 lib/stm32/g0/Makefile diff --git a/Makefile b/Makefile index 0700d91f..33443ec6 100644 --- a/Makefile +++ b/Makefile @@ -29,6 +29,7 @@ SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib)) TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \ stm32/l0 stm32/l1 stm32/l4 \ + stm32/g0 \ gd32/f1x0 \ lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 \ lm3s lm4f msp432/e4 \ diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index d3601241..62be168c 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -20,6 +20,8 @@ # include #elif defined(STM32L4) # include +#elif defined(STM32G0) +# include #elif defined(GD32F1X0) # include diff --git a/include/libopencm3/stm32/g0/irq.json b/include/libopencm3/stm32/g0/irq.json new file mode 100644 index 00000000..aa43cbc1 --- /dev/null +++ b/include/libopencm3/stm32/g0/irq.json @@ -0,0 +1,39 @@ +{ + "irqs": [ + "wwdg", + "pvd", + "rtc", + "flash", + "rcc", + "exti0_1", + "exti2_3", + "exti4_15", + "ucpd1_ucpd2", + "dma1_channel1", + "dma1_channel2_3", + "dma1_channel4_7_dmamux", + "adc_comp", + "tim1_brk_up_trg_com", + "tim1_cc", + "tim2", + "tim3", + "tim6_dac_lptim1", + "tim7_lptim2", + "tim14", + "tim15", + "tim16", + "tim17", + "i2c1", + "i2c2", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3_usart4_lpuart1", + "cec", + "aes_rng" + ], + "partname_humanreadable": "STM32 G0 series", + "partname_doxygen": "STM32G0", + "includeguard": "LIBOPENCM3_STM32_G0_NVIC_H" +} diff --git a/include/libopencm3/stm32/g0/memorymap.h b/include/libopencm3/stm32/g0/memorymap.h new file mode 100644 index 00000000..958e869d --- /dev/null +++ b/include/libopencm3/stm32/g0/memorymap.h @@ -0,0 +1,91 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +#define PERIPH_BASE (0x40000000U) +#define IOPORT_BASE (0x50000000U) +#define INFO_BASE (0x1fff7500U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define USART4_BASE (PERIPH_BASE_APB1 + 0x4C00) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800) +#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) +#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000) +#define LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400) +#define UCPD1_BASE (PERIPH_BASE_APB1 + 0xA000) +#define UCPD2_BASE (PERIPH_BASE_APB1 + 0xA400) +#define TAMP_BASE (PERIPH_BASE_APB1 + 0xB000) + +/* APB2 */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) +#define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030) +#define SYSCFG_ITLINE_BASE (PERIPH_BASE_APB2 + 0x0080) +#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200) +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) +#define TIM1_BASE (PERIPH_BASE_APB1 + 0x2C00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) +#define TIM15_BASE (PERIPH_BASE_APB1 + 0x4000) +#define TIM16_BASE (PERIPH_BASE_APB1 + 0x4400) +#define TIM17_BASE (PERIPH_BASE_APB1 + 0x4800) +#define DBGMCU_BASE (PERIPH_BASE_APB2 + 0x5800) + +/* AHB */ +#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000) +#define DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800) +#define RCC_BASE (PERIPH_BASE_AHB + 0x01000) +#define EXTI_BASE (PERIPH_BASE_AHB + 0x01800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000) +#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) +#define RNG_BASE (PERIPH_BASE_AHB + 0x05000) +#define AES_BASE (PERIPH_BASE_AHB + 0x06000) + +#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000) +#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400) +#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800) +#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00) +#define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000) +#define GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400) + +/* ST provided factory calibration values @ 3.0V */ +#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA)) +#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8)) +#define ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA)) + +#endif diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h index b9c86836..a5b64138 100644 --- a/include/libopencm3/stm32/memorymap.h +++ b/include/libopencm3/stm32/memorymap.h @@ -38,6 +38,8 @@ # include #elif defined(STM32L4) # include +#elif defined(STM32G0) +# include #elif defined(GD32F1X0) # include #else diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h index d502f8f6..f7b039e4 100644 --- a/include/libopencmsis/dispatch/irqhandlers.h +++ b/include/libopencmsis/dispatch/irqhandlers.h @@ -16,6 +16,8 @@ # include #elif defined(STM32L4) # include +#elif defined(STM32G0) +# include #elif defined(GD32F1X0) # include diff --git a/ld/devices.data b/ld/devices.data index 1962b11c..fab658cf 100644 --- a/ld/devices.data +++ b/ld/devices.data @@ -197,7 +197,6 @@ stm32l496?e* stm32l4 ROM=512K RAM=256K RAM2=64K stm32l496?g* stm32l4 ROM=1024K RAM=256K RAM2=64K stm32l4a6?g* stm32l4 ROM=1024K RAM=256K RAM2=64K - stm32ts60 stm32t ROM=32K RAM=10K stm32w108c8 stm32w ROM=64K RAM=8K @@ -205,6 +204,14 @@ stm32w108?b stm32w ROM=128K RAM=8K stm32w108cz stm32w ROM=192K RAM=12K stm32w108cc stm32w ROM=256K RAM=16K +stm32g0[43]1?4* stm32g0 ROM=16K RAM=8K +stm32g0[43]1?6* stm32g0 ROM=32K RAM=8K +stm32g0[43]1?8* stm32g0 ROM=64K RAM=8K +stm32g0[78]1?8* stm32g0 ROM=64K RAM=36K +stm32g0[78][01]?b* stm32g0 ROM=128K RAM=36K +stm32g0[BC]1?c* stm32g0 ROM=256K RAM=128K +stm32g0[BC]1?e* stm32g0 ROM=512K RAM=128K + ################################################################################ # the SAM3 chips @@ -460,6 +467,7 @@ stm32f7 END ROM_OFF=0x08000000 RAM_OFF=0x20010000 CPU=cortex-m7 FPU=hard-fpv5-sp stm32l0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft stm32l1 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft stm32l4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 RAM2_OFF=0x10000000 RAM3_OFF=0x20040000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 +stm32g0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft stm32w END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft stm32t END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 0f0d4062..c7221c87 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -16,6 +16,8 @@ # include "../stm32/l1/vector_nvic.c" #elif defined(STM32L4) # include "../stm32/l4/vector_nvic.c" +#elif defined(STM32G0) +# include "../stm32/g0/vector_nvic.c" #elif defined(GD32F1X0) # include "../gd32/f1x0/vector_nvic.c" diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile new file mode 100644 index 00000000..2893c262 --- /dev/null +++ b/lib/stm32/g0/Makefile @@ -0,0 +1,44 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2019 Guillaume Revaillot +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_stm32g0 +SRCLIBDIR ?= ../.. + +PREFIX ?= arm-none-eabi + +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m0plus -mthumb $(FP_FLAGS) \ + -ffunction-sections -fdata-sections -MD -DSTM32G0 +TGT_CFLAGS += $(DEBUG_FLAGS) +TGT_CFLAGS += $(STANDARD_FLAGS) + +ARFLAGS = rcs + +OBJS += + + +VPATH +=../:../../cm3:../common + +include ../../Makefile.include