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stm32l4: define CAN2 address and RCC bits

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This commit is contained in:
Luna Gräfje
2021-11-03 16:04:29 +01:00
parent f5813a547a
commit 9fb39ed743
2 changed files with 7 additions and 0 deletions
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1
include/libopencm3/stm32/l4/memorymap.h
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@@ -59,6 +59,7 @@
#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00) #define I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)
#define CRS_BASE (PERIPH_BASE_APB1 + 0x6000) #define CRS_BASE (PERIPH_BASE_APB1 + 0x6000)
#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) #define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800) #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)
#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00) #define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)

6
include/libopencm3/stm32/l4/rcc.h
View File

@@ -363,6 +363,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_APB1RSTR1_OPAMPRST (1 << 30) #define RCC_APB1RSTR1_OPAMPRST (1 << 30)
#define RCC_APB1RSTR1_DAC1RST (1 << 29) #define RCC_APB1RSTR1_DAC1RST (1 << 29)
#define RCC_APB1RSTR1_PWRRST (1 << 28) #define RCC_APB1RSTR1_PWRRST (1 << 28)
#define RCC_APB1RSTR1_CAN2RST (1 << 26)
#define RCC_APB1RSTR1_CAN1RST (1 << 25) #define RCC_APB1RSTR1_CAN1RST (1 << 25)
#define RCC_APB1RSTR1_I2C3RST (1 << 23) #define RCC_APB1RSTR1_I2C3RST (1 << 23)
#define RCC_APB1RSTR1_I2C2RST (1 << 22) #define RCC_APB1RSTR1_I2C2RST (1 << 22)
@@ -466,6 +467,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_APB1ENR1_OPAMPEN (1 << 30) #define RCC_APB1ENR1_OPAMPEN (1 << 30)
#define RCC_APB1ENR1_DAC1EN (1 << 29) #define RCC_APB1ENR1_DAC1EN (1 << 29)
#define RCC_APB1ENR1_PWREN (1 << 28) #define RCC_APB1ENR1_PWREN (1 << 28)
#define RCC_APB1ENR1_CAN2EN (1 << 26)
#define RCC_APB1ENR1_CAN1EN (1 << 25) #define RCC_APB1ENR1_CAN1EN (1 << 25)
#define RCC_APB1ENR1_I2C3EN (1 << 23) #define RCC_APB1ENR1_I2C3EN (1 << 23)
#define RCC_APB1ENR1_I2C2EN (1 << 22) #define RCC_APB1ENR1_I2C2EN (1 << 22)
@@ -554,6 +556,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_APB1SMENR1_OPAMPSMEN (1 << 30) #define RCC_APB1SMENR1_OPAMPSMEN (1 << 30)
#define RCC_APB1SMENR1_DAC1SMEN (1 << 29) #define RCC_APB1SMENR1_DAC1SMEN (1 << 29)
#define RCC_APB1SMENR1_PWRSMEN (1 << 28) #define RCC_APB1SMENR1_PWRSMEN (1 << 28)
#define RCC_APB1SMENR1_CAN2SMEN (1 << 26)
#define RCC_APB1SMENR1_CAN1SMEN (1 << 25) #define RCC_APB1SMENR1_CAN1SMEN (1 << 25)
#define RCC_APB1SMENR1_I2C3SMEN (1 << 23) #define RCC_APB1SMENR1_I2C3SMEN (1 << 23)
#define RCC_APB1SMENR1_I2C2SMEN (1 << 22) #define RCC_APB1SMENR1_I2C2SMEN (1 << 22)
@@ -778,6 +781,7 @@ enum rcc_periph_clken {
RCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29), RCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29),
RCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28), RCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28),
RCC_USB = _REG_BIT(RCC_APB1ENR1_OFFSET, 26), RCC_USB = _REG_BIT(RCC_APB1ENR1_OFFSET, 26),
RCC_CAN2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 26),
RCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25), RCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25),
RCC_CRS = _REG_BIT(RCC_APB1ENR1_OFFSET, 24), RCC_CRS = _REG_BIT(RCC_APB1ENR1_OFFSET, 24),
RCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23), RCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23),
@@ -849,6 +853,7 @@ enum rcc_periph_clken {
SCC_OPAMP = _REG_BIT(RCC_APB1ENR1_OFFSET, 30), SCC_OPAMP = _REG_BIT(RCC_APB1ENR1_OFFSET, 30),
SCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29), SCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29),
SCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28), SCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28),
SCC_CAN2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 26),
SCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25), SCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25),
SCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23), SCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23),
SCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22), SCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22),
@@ -920,6 +925,7 @@ enum rcc_periph_rst {
RST_DAC1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 29), RST_DAC1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 29),
RST_PWR = _REG_BIT(RCC_APB1RSTR1_OFFSET, 28), RST_PWR = _REG_BIT(RCC_APB1RSTR1_OFFSET, 28),
RST_USB = _REG_BIT(RCC_APB1RSTR1_OFFSET, 26), RST_USB = _REG_BIT(RCC_APB1RSTR1_OFFSET, 26),
RST_CAN2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 26),
RST_CAN1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 25), RST_CAN1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 25),
RST_CRS = _REG_BIT(RCC_APB1RSTR1_OFFSET, 24), RST_CRS = _REG_BIT(RCC_APB1RSTR1_OFFSET, 24),
RST_I2C3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 23), RST_I2C3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 23),