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stm32: rcc: convert to use new standard defines

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This commit is contained in:
Karl Palsson
2020-10-18 15:08:33 +00:00
parent c7d7a18dd7
commit 76c0a8c289
7 changed files with 137 additions and 137 deletions
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36
lib/stm32/l1/rcc.c
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@@ -53,9 +53,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
.pll_mul = RCC_CFGR_PLLMUL_MUL3,
.pll_div = RCC_CFGR_PLLDIV_DIV2,
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_NODIV,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_waitstates = 1,
.ahb_frequency = 24000000,
@@ -66,9 +66,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
.pll_mul = RCC_CFGR_PLLMUL_MUL6,
.pll_div = RCC_CFGR_PLLDIV_DIV3,
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_NODIV,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_waitstates = 1,
.ahb_frequency = 32000000,
@@ -76,9 +76,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.apb2_frequency = 32000000,
},
{ /* 16MHz HSI raw */
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_NODIV,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_waitstates = 0,
.ahb_frequency = 16000000,
@@ -86,9 +86,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.apb2_frequency = 16000000,
},
{ /* 4MHz HSI raw */
.hpre = RCC_CFGR_HPRE_SYSCLK_DIV4,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.hpre = RCC_CFGR_HPRE_DIV4,
.ppre1 = RCC_CFGR_PPRE_NODIV,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_waitstates = 0,
.ahb_frequency = 4000000,
@@ -96,9 +96,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.apb2_frequency = 4000000,
},
{ /* 4MHz MSI raw */
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_NODIV,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_waitstates = 0,
.ahb_frequency = 4194000,
@@ -107,9 +107,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
},
{ /* 2MHz MSI raw */
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_NODIV,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_waitstates = 0,
.ahb_frequency = 2097000,