diff --git a/lib/gd32/f1x0/rcc.c b/lib/gd32/f1x0/rcc.c index 729a71eb..867079dc 100644 --- a/lib/gd32/f1x0/rcc.c +++ b/lib/gd32/f1x0/rcc.c @@ -62,10 +62,10 @@ uint32_t rcc_ahb_frequency = 8000000; const struct rcc_clock_scale rcc_hsi_configs[] = { { /* 48MHz */ .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL12, - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, - .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, + .adcpre = RCC_CFGR_ADCPRE_DIV8, .use_hse = false, .ahb_frequency = 48000000, .apb1_frequency = 24000000, @@ -73,10 +73,10 @@ const struct rcc_clock_scale rcc_hsi_configs[] = { }, { /* 64MHz */ .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL16, - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, - .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, + .adcpre = RCC_CFGR_ADCPRE_DIV8, .use_hse = false, .ahb_frequency = 64000000, .apb1_frequency = 32000000, @@ -87,10 +87,10 @@ const struct rcc_clock_scale rcc_hsi_configs[] = { const struct rcc_clock_scale rcc_hse8_configs[] = { { /* 72MHz */ .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL9, - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, - .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, + .adcpre = RCC_CFGR_ADCPRE_DIV8, .usbpre = RCC_CFGR_USBPRE_PLL_CLK_DIV1_5, .use_hse = true, .pll_hse_prediv = RCC_CFGR2_PREDIV_NODIV, diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index bab64b51..ddd24e6a 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -631,10 +631,10 @@ void rcc_clock_setup_in_hsi_out_64mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 64MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV8); /* Set. 8MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 32MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 64MHz Max. 72MHz */ /* * Sysclk is running with 64MHz -> 2 waitstates. @@ -684,10 +684,10 @@ void rcc_clock_setup_in_hsi_out_48mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /*Set.48MHz Max.72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /*Set. 6MHz Max.14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /*Set.24MHz Max.36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /*Set.48MHz Max.72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /*Set.48MHz Max.72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV8); /*Set. 6MHz Max.14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /*Set.24MHz Max.36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /*Set.48MHz Max.72MHz */ rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /*Set.48MHz Max.48MHz */ /* @@ -738,10 +738,10 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 24MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 12MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 24MHz Max. 24MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV2); /* Set. 12MHz Max. 12MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 24MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 24MHz */ /* * Sysclk is (will be) running with 24MHz -> 0 waitstates. @@ -796,10 +796,10 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 24MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV2); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 72MHz */ /* * Sysclk runs with 24MHz -> 0 waitstates. @@ -860,10 +860,10 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV8); /* Set. 9MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. @@ -924,10 +924,10 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. @@ -988,10 +988,10 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. @@ -1053,10 +1053,10 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void) * Set prescalers for AHB, ADC, APB1, APB2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */ /* Set pll2 prediv and multiplier */ rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5); diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index bb091f6a..80db1935 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -54,9 +54,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .plln = 240, .pllp = 2, .pllq = 5, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 30000000, diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c index 75e92647..9d5fc6d5 100644 --- a/lib/stm32/f3/rcc.c +++ b/lib/stm32/f3/rcc.c @@ -48,9 +48,9 @@ const struct rcc_clock_scale rcc_hsi_configs[] = { { /* 48MHz */ .pllmul = RCC_CFGR_PLLMUL_MUL12, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE1_DIV_2, - .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .flash_waitstates = 1, .ahb_frequency = 48000000, .apb1_frequency = 24000000, @@ -59,9 +59,9 @@ const struct rcc_clock_scale rcc_hsi_configs[] = { { /* 64MHz */ .pllmul = RCC_CFGR_PLLMUL_MUL16, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE1_DIV_2, - .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .flash_waitstates = 2, .ahb_frequency = 64000000, .apb1_frequency = 32000000, @@ -76,9 +76,9 @@ const struct rcc_clock_scale rcc_hse8mhz_configs[] = { .plldiv = RCC_CFGR2_PREDIV_NODIV, .usbdiv1 = false, .flash_waitstates = 2, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE1_DIV_2, - .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .ahb_frequency = 72e6, .apb1_frequency = 36e6, .apb2_frequency = 72e6, diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index f729312c..ba3f2469 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -57,9 +57,9 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, @@ -74,9 +74,9 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -91,9 +91,9 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { .pllq = 8, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -111,9 +111,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, @@ -128,9 +128,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -145,9 +145,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 8, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -165,9 +165,9 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, @@ -182,9 +182,9 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -199,9 +199,9 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 8, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -219,9 +219,9 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, @@ -236,9 +236,9 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -253,9 +253,9 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 8, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -273,9 +273,9 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, @@ -290,9 +290,9 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 7, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, @@ -307,9 +307,9 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllq = 8, .pllr = 0, .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, diff --git a/lib/stm32/f7/rcc.c b/lib/stm32/f7/rcc.c index b95545d8..4246036a 100644 --- a/lib/stm32/f7/rcc.c +++ b/lib/stm32/f7/rcc.c @@ -25,9 +25,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = { .plln = 432, .pllp = 2, .pllq = 9, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .vos_scale = PWR_SCALE1, .overdrive = 1, .flash_waitstates = 7, @@ -39,9 +39,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = { .plln = 336, .pllp = 2, .pllq = 7, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .vos_scale = PWR_SCALE2, .overdrive = 1, .flash_waitstates = 5, @@ -53,9 +53,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = { .plln = 240, .pllp = 2, .pllq = 5, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .vos_scale = PWR_SCALE3, .overdrive = 0, .flash_waitstates = 3, @@ -67,9 +67,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = { .plln = 144, .pllp = 2, .pllq = 3, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, .vos_scale = PWR_SCALE3, .overdrive = 0, .flash_waitstates = 2, @@ -81,9 +81,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = { .plln = 192, .pllp = 4, .pllq = 4, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, - .ppre2 = RCC_CFGR_PPRE_DIV_2, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV2, + .ppre2 = RCC_CFGR_PPRE_DIV2, .vos_scale = PWR_SCALE3, .overdrive = 0, .flash_waitstates = 1, @@ -95,9 +95,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = { .plln = 192, .pllp = 8, .pllq = 4, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_NONE, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_NODIV, + .ppre2 = RCC_CFGR_PPRE_NODIV, .vos_scale = PWR_SCALE3, .overdrive = 0, .flash_waitstates = 0, diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index 5865abbb..06898d00 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -53,9 +53,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, .pll_mul = RCC_CFGR_PLLMUL_MUL3, .pll_div = RCC_CFGR_PLLDIV_DIV2, - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_NODIV, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_waitstates = 1, .ahb_frequency = 24000000, @@ -66,9 +66,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, .pll_mul = RCC_CFGR_PLLMUL_MUL6, .pll_div = RCC_CFGR_PLLDIV_DIV3, - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_NODIV, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_waitstates = 1, .ahb_frequency = 32000000, @@ -76,9 +76,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { .apb2_frequency = 32000000, }, { /* 16MHz HSI raw */ - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_NODIV, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_waitstates = 0, .ahb_frequency = 16000000, @@ -86,9 +86,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { .apb2_frequency = 16000000, }, { /* 4MHz HSI raw */ - .hpre = RCC_CFGR_HPRE_SYSCLK_DIV4, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .hpre = RCC_CFGR_HPRE_DIV4, + .ppre1 = RCC_CFGR_PPRE_NODIV, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_waitstates = 0, .ahb_frequency = 4000000, @@ -96,9 +96,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { .apb2_frequency = 4000000, }, { /* 4MHz MSI raw */ - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_NODIV, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_waitstates = 0, .ahb_frequency = 4194000, @@ -107,9 +107,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { .msi_range = RCC_ICSCR_MSIRANGE_4MHZ, }, { /* 2MHz MSI raw */ - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_NODIV, + .ppre2 = RCC_CFGR_PPRE_NODIV, .voltage_scale = PWR_SCALE1, .flash_waitstates = 0, .ahb_frequency = 2097000,