stm32: rcc: convert to use new standard defines

This commit is contained in:
Karl Palsson
2020-10-18 15:08:33 +00:00
parent c7d7a18dd7
commit 76c0a8c289
7 changed files with 137 additions and 137 deletions

View File

@@ -25,9 +25,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
.plln = 432,
.pllp = 2,
.pllq = 9,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV4,
.ppre2 = RCC_CFGR_PPRE_DIV2,
.vos_scale = PWR_SCALE1,
.overdrive = 1,
.flash_waitstates = 7,
@@ -39,9 +39,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV4,
.ppre2 = RCC_CFGR_PPRE_DIV2,
.vos_scale = PWR_SCALE2,
.overdrive = 1,
.flash_waitstates = 5,
@@ -53,9 +53,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV4,
.ppre2 = RCC_CFGR_PPRE_DIV2,
.vos_scale = PWR_SCALE3,
.overdrive = 0,
.flash_waitstates = 3,
@@ -67,9 +67,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
.plln = 144,
.pllp = 2,
.pllq = 3,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV4,
.ppre2 = RCC_CFGR_PPRE_DIV2,
.vos_scale = PWR_SCALE3,
.overdrive = 0,
.flash_waitstates = 2,
@@ -81,9 +81,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
.plln = 192,
.pllp = 4,
.pllq = 4,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_2,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV2,
.ppre2 = RCC_CFGR_PPRE_DIV2,
.vos_scale = PWR_SCALE3,
.overdrive = 0,
.flash_waitstates = 1,
@@ -95,9 +95,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
.plln = 192,
.pllp = 8,
.pllq = 4,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_NONE,
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_NODIV,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.vos_scale = PWR_SCALE3,
.overdrive = 0,
.flash_waitstates = 0,