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stm32: rcc: convert to use new standard defines

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This commit is contained in:
Karl Palsson
2020-10-18 15:08:33 +00:00
parent c7d7a18dd7
commit 76c0a8c289
7 changed files with 137 additions and 137 deletions
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24
lib/gd32/f1x0/rcc.c
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@@ -62,10 +62,10 @@ uint32_t rcc_ahb_frequency = 8000000;
const struct rcc_clock_scale rcc_hsi_configs[] = {
{ /* 48MHz */
.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL12,
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV2,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.adcpre = RCC_CFGR_ADCPRE_DIV8,
.use_hse = false,
.ahb_frequency = 48000000,
.apb1_frequency = 24000000,
@@ -73,10 +73,10 @@ const struct rcc_clock_scale rcc_hsi_configs[] = {
},
{ /* 64MHz */
.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL16,
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV2,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.adcpre = RCC_CFGR_ADCPRE_DIV8,
.use_hse = false,
.ahb_frequency = 64000000,
.apb1_frequency = 32000000,
@@ -87,10 +87,10 @@ const struct rcc_clock_scale rcc_hsi_configs[] = {
const struct rcc_clock_scale rcc_hse8_configs[] = {
{ /* 72MHz */
.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL9,
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV2,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.adcpre = RCC_CFGR_ADCPRE_DIV8,
.usbpre = RCC_CFGR_USBPRE_PLL_CLK_DIV1_5,
.use_hse = true,
.pll_hse_prediv = RCC_CFGR2_PREDIV_NODIV,