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stm32/g0: rcc: Correct RCC_CCIPR_TIM1SEL_SHIFT value (20 -> 22)

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Reviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
Evgenii Iarkov
2022-02-01 21:41:20 +02:00
committed by Karl Palsson
parent 3f52b7784c
commit 72d4064744
1 changed files with 1 additions and 1 deletions
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2
include/libopencm3/stm32/g0/rcc.h
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@@ -487,7 +487,7 @@
/**@}*/ /**@}*/
#define RCC_CCIPR_TIM1SEL_MASK 0x1 #define RCC_CCIPR_TIM1SEL_MASK 0x1
#define RCC_CCIPR_TIM1SEL_SHIFT 20 #define RCC_CCIPR_TIM1SEL_SHIFT 22
/** @defgroup rcc_ccipr_tim1sel TIM1SEL /** @defgroup rcc_ccipr_tim1sel TIM1SEL
@{*/ @{*/
#define RCC_CCIPR_TIM1SEL_TIMPCLK 0 #define RCC_CCIPR_TIM1SEL_TIMPCLK 0