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stm32l0: add missing base addresses for usart4/5, gpioe

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Reported-by: massic@irc
Fixes: 623fabca5f when we initially added these extra periphs
This commit is contained in:
Karl Palsson
2021-04-28 10:34:47 +00:00
parent fe52fcdb1a
commit 4f71527881
2 changed files with 4 additions and 0 deletions
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1
include/libopencm3/stm32/l0/gpio.h
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@@ -46,6 +46,7 @@
#define GPIOB_BRR GPIO_BRR(GPIOB)
#define GPIOC_BRR GPIO_BRR(GPIOC)
#define GPIOD_BRR GPIO_BRR(GPIOD)
#define GPIOE_BRR GPIO_BRR(GPIOE)
#define GPIOH_BRR GPIO_BRR(GPIOH)
/*****************************************************************************/

3
include/libopencm3/stm32/l0/memorymap.h
View File

@@ -45,6 +45,8 @@
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x4800)
#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000)
#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
@@ -80,6 +82,7 @@
#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)
#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)
#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)
#define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)
#define GPIO_PORT_H_BASE (IOPORT_BASE + 0x01C00)
/* Device Electronic Signature */