Add generated bit/shift/mask #defines for CGU, CREG, RGU, USB (USB0 only) peripherals.
Added script used to generate #defines above. Fixed one small change in the #define naming scheme in i2c0_init().
This commit is contained in:
Jared Boone
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
49b2be5224
commit
24d8d81b43
@@ -179,61 +179,710 @@ LGPL License Terms @ref lgpl_license
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/* Output stage 27 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
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/* --- CGU_XTAL_OSC_CTRL values -------------------------------------------- */
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/* --- CGU_FREQ_MON values -------------------------------------- */
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#define CGU_XTAL_OSC_CTRL_ENABLE (1 << 0) /* enable or power down xtal osc */
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#define CGU_XTAL_OSC_CTRL_BYPASS (1 << 1) /* external clock input (not xtal) */
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#define CGU_XTAL_OSC_CTRL_HF (1 << 2) /* high frequency mode (>15 MHz) */
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/* RCNT: 9-bit reference clock-counter value */
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#define CGU_FREQ_MON_RCNT_SHIFT (0)
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#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)
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#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)
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/* --- CGU_PLL1_STAT values ------------------------------------------------ */
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/* FCNT: 14-bit selected clock-counter value */
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#define CGU_FREQ_MON_FCNT_SHIFT (9)
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#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)
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#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)
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#define CGU_PLL1_STAT_LOCK (1 << 0)
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/* MEAS: Measure frequency */
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#define CGU_FREQ_MON_MEAS_SHIFT (23)
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#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)
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/* --- CGU_PLL1_CTRL values ------------------------------------------------ */
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/* CLK_SEL: Clock-source selection for the clock to be measured */
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#define CGU_FREQ_MON_CLK_SEL_SHIFT (24)
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#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)
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#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)
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#define CGU_PLL1_CTRL_PD (1 << 0) /* power down */
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#define CGU_PLL1_CTRL_BYPASS (1 << 1) /* PLL input to post-dividers */
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#define CGU_PLL1_CTRL_FBSEL (1 << 6) /* use clkout as feedback input */
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#define CGU_PLL1_CTRL_DIRECT (1 << 7) /* enable direct CCO output */
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#define CGU_PLL1_CTRL_PSEL_SHIFT 8 /* division ratio P (2 bits) */
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#define CGU_PLL1_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */
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#define CGU_PLL1_CTRL_NSEL_SHIFT 12 /* division ratio N (2 bits) */
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#define CGU_PLL1_CTRL_MSEL_SHIFT 16 /* division ratio M (8 bits) */
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#define CGU_PLL1_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */
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/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */
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/* --- CGU_PLL0USB_STAT values --------------------------------------------- */
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/* ENABLE: Oscillator-pad enable */
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#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)
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#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)
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#define CGU_PLL0USB_STAT_LOCK (1 << 0) /* PLL0 lock indicator */
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#define CGU_PLL0USB_STAT_FR (1 << 1) /* PLL0 free running indicator */
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/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */
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#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)
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#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)
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/* --- CGU_PLL0USB_CTRL values --------------------------------------------- */
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/* HF: Select frequency range */
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#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2)
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#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)
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#define CGU_PLL0USB_CTRL_PD (1 << 0) /* power down */
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#define CGU_PLL0USB_CTRL_BYPASS (1 << 1) /* input to post-dividers */
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#define CGU_PLL0USB_CTRL_DIRECTI (1 << 2) /* direct input */
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#define CGU_PLL0USB_CTRL_DIRECTO (1 << 3) /* direct output */
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#define CGU_PLL0USB_CTRL_CLKEN (1 << 4) /* clock enable */
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#define CGU_PLL0USB_CTRL_FRM (1 << 6) /* free running mode */
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#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */
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#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */
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/* --- CGU_PLL0USB_STAT values ---------------------------------- */
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/* --- CGU_PLL0USB_MDIV values --------------------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0USB_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)
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#define CGU_PLL0USB_MDIV_MDEC_SHIFT 0 /* Decoded M-divider value (17 bits) */
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#define CGU_PLL0USB_SELP_MDEC_SHIFT 17 /* Bandwidth select P value (5 bits) */
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#define CGU_PLL0USB_SELI_MDEC_SHIFT 22 /* Bandwidth select I value (6 bits) */
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#define CGU_PLL0USB_SELR_MDEC_SHIFT 28 /* Bandwidth select R value (4 bits) */
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0USB_STAT_FR_SHIFT (1)
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#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)
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/* --- CGU_PLL0USB_NP_DIV values ------------------------------------------- */
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/* --- CGU_PLL0USB_CTRL values ---------------------------------- */
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#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT 0 /* Decoded P-divider value (7 bits) */
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#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT 12 /* Decoded N-divider value (8 bits) */
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/* PD: PLL0 power down */
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#define CGU_PLL0USB_CTRL_PD_SHIFT (0)
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#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)
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/* --- CGU_BASE_x_CLK values ----------------------------------------------- */
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)
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#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */
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#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */
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#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0USB_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0USB_MDIV values ---------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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/* SELP: Bandwidth select P value */
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#define CGU_PLL0USB_MDIV_SELP_SHIFT (17)
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#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)
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#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)
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/* SELI: Bandwidth select I value */
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#define CGU_PLL0USB_MDIV_SELI_SHIFT (22)
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#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)
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#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)
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/* SELR: Bandwidth select R value */
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#define CGU_PLL0USB_MDIV_SELR_SHIFT (28)
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#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)
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#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)
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/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1)
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#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)
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/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */
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/* PD: PLL0 power down */
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#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0)
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#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)
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/* PLLFRACT_REQ: Fractional PLL word write request */
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)
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/* SEL_EXT: Select fractional divider */
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)
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/* MOD_PD: Sigma-Delta modulator power-down */
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#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)
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#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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#define CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */
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/* PLLFRACT_CTRL: PLL fractional divider control word */
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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/* --- CGU_PLL1_STAT values ------------------------------------- */
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/* LOCK: PLL1 lock indicator */
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#define CGU_PLL1_STAT_LOCK_SHIFT (0)
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#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)
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/* --- CGU_PLL1_CTRL values ------------------------------------- */
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/* PD: PLL1 power down */
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#define CGU_PLL1_CTRL_PD_SHIFT (0)
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#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL1_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)
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/* FBSEL: PLL feedback select */
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#define CGU_PLL1_CTRL_FBSEL_SHIFT (6)
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#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)
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/* DIRECT: PLL direct CCO output */
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#define CGU_PLL1_CTRL_DIRECT_SHIFT (7)
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#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)
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/* PSEL: Post-divider division ratio P */
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#define CGU_PLL1_CTRL_PSEL_SHIFT (8)
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#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)
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#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)
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/* NSEL: Pre-divider division ratio N */
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#define CGU_PLL1_CTRL_NSEL_SHIFT (12)
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#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)
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#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)
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/* MSEL: Feedback-divider division ratio (M) */
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#define CGU_PLL1_CTRL_MSEL_SHIFT (16)
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#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)
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#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)
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/* CLK_SEL: Clock-source selection */
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#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVA_CTRL values ------------------------------------ */
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/* PD: Integer divider power down */
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#define CGU_IDIVA_CTRL_PD_SHIFT (0)
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#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)
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/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */
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#define CGU_IDIVA_CTRL_IDIV_SHIFT (2)
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#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)
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#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
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#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVB_CTRL values ------------------------------------ */
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/* PD: Integer divider power down */
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#define CGU_IDIVB_CTRL_PD_SHIFT (0)
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#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)
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|
||||
/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVB_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_IDIVC_CTRL values ------------------------------------ */
|
||||
|
||||
/* PD: Integer divider power down */
|
||||
#define CGU_IDIVC_CTRL_PD_SHIFT (0)
|
||||
#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)
|
||||
|
||||
/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVC_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_IDIVD_CTRL values ------------------------------------ */
|
||||
|
||||
/* PD: Integer divider power down */
|
||||
#define CGU_IDIVD_CTRL_PD_SHIFT (0)
|
||||
#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)
|
||||
|
||||
/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVD_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_IDIVE_CTRL values ------------------------------------ */
|
||||
|
||||
/* PD: Integer divider power down */
|
||||
#define CGU_IDIVE_CTRL_PD_SHIFT (0)
|
||||
#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)
|
||||
|
||||
/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVE_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SAFE_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SAFE_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_USB0_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_USB0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_USB1_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_USB1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_M4_CLK values ----------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_M4_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SPI_CLK values ---------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SPI_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_APB1_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_APB1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_APB3_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_APB3_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_LCD_CLK values ---------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_LCD_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_VADC_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_VADC_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SDIO_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SDIO_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SSP0_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SSP0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SSP1_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SSP1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_UART0_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
|
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#define CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
|
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|
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/* --- CGU_BASE_UART1_CLK values -------------------------------- */
|
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|
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/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART1_CLK_PD_SHIFT (0)
|
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#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)
|
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|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)
|
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#define CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
|
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|
||||
/* --- CGU_BASE_UART2_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART2_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_UART3_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART3_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_OUT_CLK values ---------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_OUT_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_APLL_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_APLL_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user