From 24d8d81b436e5360a3f9542b7eb95f4179396395 Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Thu, 27 Sep 2012 16:57:34 -0700 Subject: [PATCH] Add generated bit/shift/mask #defines for CGU, CREG, RGU, USB (USB0 only) peripherals. Added script used to generate #defines above. Fixed one small change in the #define naming scheme in i2c0_init(). --- include/libopencm3/lpc43xx/cgu.h | 729 +++++++++++++++++++-- include/libopencm3/lpc43xx/creg.h | 243 +++++++ include/libopencm3/lpc43xx/rgu.h | 879 +++++++++++++++++++++++++ include/libopencm3/lpc43xx/usb.h | 1020 +++++++++++++++++++++++++++++ lib/lpc43xx/i2c.c | 2 +- scripts/data/lpc43xx/gen.py | 54 ++ 6 files changed, 2886 insertions(+), 41 deletions(-) create mode 100644 scripts/data/lpc43xx/gen.py diff --git a/include/libopencm3/lpc43xx/cgu.h b/include/libopencm3/lpc43xx/cgu.h index 915150b2..597f3f38 100644 --- a/include/libopencm3/lpc43xx/cgu.h +++ b/include/libopencm3/lpc43xx/cgu.h @@ -179,61 +179,710 @@ LGPL License Terms @ref lgpl_license /* Output stage 27 control CLK register for base clock */ #define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) -/* --- CGU_XTAL_OSC_CTRL values -------------------------------------------- */ +/* --- CGU_FREQ_MON values -------------------------------------- */ -#define CGU_XTAL_OSC_CTRL_ENABLE (1 << 0) /* enable or power down xtal osc */ -#define CGU_XTAL_OSC_CTRL_BYPASS (1 << 1) /* external clock input (not xtal) */ -#define CGU_XTAL_OSC_CTRL_HF (1 << 2) /* high frequency mode (>15 MHz) */ +/* RCNT: 9-bit reference clock-counter value */ +#define CGU_FREQ_MON_RCNT_SHIFT (0) +#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) +#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) -/* --- CGU_PLL1_STAT values ------------------------------------------------ */ +/* FCNT: 14-bit selected clock-counter value */ +#define CGU_FREQ_MON_FCNT_SHIFT (9) +#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) +#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) -#define CGU_PLL1_STAT_LOCK (1 << 0) +/* MEAS: Measure frequency */ +#define CGU_FREQ_MON_MEAS_SHIFT (23) +#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) -/* --- CGU_PLL1_CTRL values ------------------------------------------------ */ +/* CLK_SEL: Clock-source selection for the clock to be measured */ +#define CGU_FREQ_MON_CLK_SEL_SHIFT (24) +#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) +#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) -#define CGU_PLL1_CTRL_PD (1 << 0) /* power down */ -#define CGU_PLL1_CTRL_BYPASS (1 << 1) /* PLL input to post-dividers */ -#define CGU_PLL1_CTRL_FBSEL (1 << 6) /* use clkout as feedback input */ -#define CGU_PLL1_CTRL_DIRECT (1 << 7) /* enable direct CCO output */ -#define CGU_PLL1_CTRL_PSEL_SHIFT 8 /* division ratio P (2 bits) */ -#define CGU_PLL1_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */ -#define CGU_PLL1_CTRL_NSEL_SHIFT 12 /* division ratio N (2 bits) */ -#define CGU_PLL1_CTRL_MSEL_SHIFT 16 /* division ratio M (8 bits) */ -#define CGU_PLL1_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */ +/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */ -/* --- CGU_PLL0USB_STAT values --------------------------------------------- */ +/* ENABLE: Oscillator-pad enable */ +#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) +#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) -#define CGU_PLL0USB_STAT_LOCK (1 << 0) /* PLL0 lock indicator */ -#define CGU_PLL0USB_STAT_FR (1 << 1) /* PLL0 free running indicator */ +/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */ +#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) +#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) -/* --- CGU_PLL0USB_CTRL values --------------------------------------------- */ +/* HF: Select frequency range */ +#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2) +#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) -#define CGU_PLL0USB_CTRL_PD (1 << 0) /* power down */ -#define CGU_PLL0USB_CTRL_BYPASS (1 << 1) /* input to post-dividers */ -#define CGU_PLL0USB_CTRL_DIRECTI (1 << 2) /* direct input */ -#define CGU_PLL0USB_CTRL_DIRECTO (1 << 3) /* direct output */ -#define CGU_PLL0USB_CTRL_CLKEN (1 << 4) /* clock enable */ -#define CGU_PLL0USB_CTRL_FRM (1 << 6) /* free running mode */ -#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */ -#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */ +/* --- CGU_PLL0USB_STAT values ---------------------------------- */ -/* --- CGU_PLL0USB_MDIV values --------------------------------------------- */ +/* LOCK: PLL0 lock indicator */ +#define CGU_PLL0USB_STAT_LOCK_SHIFT (0) +#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) -#define CGU_PLL0USB_MDIV_MDEC_SHIFT 0 /* Decoded M-divider value (17 bits) */ -#define CGU_PLL0USB_SELP_MDEC_SHIFT 17 /* Bandwidth select P value (5 bits) */ -#define CGU_PLL0USB_SELI_MDEC_SHIFT 22 /* Bandwidth select I value (6 bits) */ -#define CGU_PLL0USB_SELR_MDEC_SHIFT 28 /* Bandwidth select R value (4 bits) */ +/* FR: PLL0 free running indicator */ +#define CGU_PLL0USB_STAT_FR_SHIFT (1) +#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) -/* --- CGU_PLL0USB_NP_DIV values ------------------------------------------- */ +/* --- CGU_PLL0USB_CTRL values ---------------------------------- */ -#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT 0 /* Decoded P-divider value (7 bits) */ -#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT 12 /* Decoded N-divider value (8 bits) */ +/* PD: PLL0 power down */ +#define CGU_PLL0USB_CTRL_PD_SHIFT (0) +#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) -/* --- CGU_BASE_x_CLK values ----------------------------------------------- */ +/* BYPASS: Input clock bypass control */ +#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) -#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */ -#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */ -#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ +/* DIRECTI: PLL0 direct input */ +#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) +#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) + +/* DIRECTO: PLL0 direct output */ +#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) +#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) + +/* CLKEN: PLL0 clock enable */ +#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) + +/* FRM: Free running mode */ +#define CGU_PLL0USB_CTRL_FRM_SHIFT (6) +#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_PLL0USB_MDIV values ---------------------------------- */ + +/* MDEC: Decoded M-divider coefficient value */ +#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) +#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) + +/* SELP: Bandwidth select P value */ +#define CGU_PLL0USB_MDIV_SELP_SHIFT (17) +#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) +#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) + +/* SELI: Bandwidth select I value */ +#define CGU_PLL0USB_MDIV_SELI_SHIFT (22) +#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) +#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) + +/* SELR: Bandwidth select R value */ +#define CGU_PLL0USB_MDIV_SELR_SHIFT (28) +#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) +#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) + +/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */ + +/* PDEC: Decoded P-divider coefficient value */ +#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) + +/* NDEC: Decoded N-divider coefficient value */ +#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) + +/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */ + +/* LOCK: PLL0 lock indicator */ +#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) +#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) + +/* FR: PLL0 free running indicator */ +#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1) +#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) + +/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */ + +/* PD: PLL0 power down */ +#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) +#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) + +/* DIRECTI: PLL0 direct input */ +#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2) +#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) + +/* DIRECTO: PLL0 direct output */ +#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3) +#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) + +/* CLKEN: PLL0 clock enable */ +#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) + +/* FRM: Free running mode */ +#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) +#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) + +/* PLLFRACT_REQ: Fractional PLL word write request */ +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12) +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) + +/* SEL_EXT: Select fractional divider */ +#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13) +#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) + +/* MOD_PD: Sigma-Delta modulator power-down */ +#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14) +#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */ + +/* MDEC: Decoded M-divider coefficient value */ +#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) +#define CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) + +/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */ + +/* PDEC: Decoded P-divider coefficient value */ +#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) + +/* NDEC: Decoded N-divider coefficient value */ +#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) + +/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */ + +/* PLLFRACT_CTRL: PLL fractional divider control word */ +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) + +/* --- CGU_PLL1_STAT values ------------------------------------- */ + +/* LOCK: PLL1 lock indicator */ +#define CGU_PLL1_STAT_LOCK_SHIFT (0) +#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) + +/* --- CGU_PLL1_CTRL values ------------------------------------- */ + +/* PD: PLL1 power down */ +#define CGU_PLL1_CTRL_PD_SHIFT (0) +#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL1_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) + +/* FBSEL: PLL feedback select */ +#define CGU_PLL1_CTRL_FBSEL_SHIFT (6) +#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) + +/* DIRECT: PLL direct CCO output */ +#define CGU_PLL1_CTRL_DIRECT_SHIFT (7) +#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) + +/* PSEL: Post-divider division ratio P */ +#define CGU_PLL1_CTRL_PSEL_SHIFT (8) +#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) +#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) + +/* NSEL: Pre-divider division ratio N */ +#define CGU_PLL1_CTRL_NSEL_SHIFT (12) +#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) +#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) + +/* MSEL: Feedback-divider division ratio (M) */ +#define CGU_PLL1_CTRL_MSEL_SHIFT (16) +#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) +#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) + +/* CLK_SEL: Clock-source selection */ +#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVA_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVA_CTRL_PD_SHIFT (0) +#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) + +/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */ +#define CGU_IDIVA_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) +#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVB_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVB_CTRL_PD_SHIFT (0) +#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) + +/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */ +#define CGU_IDIVB_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) +#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVC_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVC_CTRL_PD_SHIFT (0) +#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) + +/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */ +#define CGU_IDIVC_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) +#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVD_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVD_CTRL_PD_SHIFT (0) +#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) + +/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */ +#define CGU_IDIVD_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) +#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVE_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVE_CTRL_PD_SHIFT (0) +#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) + +/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */ +#define CGU_IDIVE_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) +#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SAFE_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SAFE_CLK_PD_SHIFT (0) +#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_USB0_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_USB0_CLK_PD_SHIFT (0) +#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0) +#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_USB1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_USB1_CLK_PD_SHIFT (0) +#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_M4_CLK values ----------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_M4_CLK_PD_SHIFT (0) +#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SPI_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SPI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APB1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APB1_CLK_PD_SHIFT (0) +#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APB3_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APB3_CLK_PD_SHIFT (0) +#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_LCD_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_LCD_CLK_PD_SHIFT (0) +#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_VADC_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_VADC_CLK_PD_SHIFT (0) +#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SDIO_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SDIO_CLK_PD_SHIFT (0) +#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SSP0_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SSP0_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SSP1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SSP1_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART0_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART0_CLK_PD_SHIFT (0) +#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART1_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART1_CLK_PD_SHIFT (0) +#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART2_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART2_CLK_PD_SHIFT (0) +#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART3_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART3_CLK_PD_SHIFT (0) +#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_OUT_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_OUT_CLK_PD_SHIFT (0) +#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APLL_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APLL_CLK_PD_SHIFT (0) +#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ diff --git a/include/libopencm3/lpc43xx/creg.h b/include/libopencm3/lpc43xx/creg.h index 89f4e565..7b5cac1b 100644 --- a/include/libopencm3/lpc43xx/creg.h +++ b/include/libopencm3/lpc43xx/creg.h @@ -102,6 +102,249 @@ LGPL License Terms @ref lgpl_license /* USB1 frame length adjust register */ #define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600) +/* --- CREG_CREG0 values ---------------------------------------- */ + +/* EN1KHZ: Enable 1 kHz output */ +#define CREG_CREG0_EN1KHZ_SHIFT (0) +#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT) + +/* EN32KHZ: Enable 32 kHz output */ +#define CREG_CREG0_EN32KHZ_SHIFT (1) +#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT) + +/* RESET32KHZ: 32 kHz oscillator reset */ +#define CREG_CREG0_RESET32KHZ_SHIFT (2) +#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT) + +/* PD32KHZ: 32 kHz power control */ +#define CREG_CREG0_PD32KHZ_SHIFT (3) +#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT) + +/* USB0PHY: USB0 PHY power control */ +#define CREG_CREG0_USB0PHY_SHIFT (5) +#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT) + +/* ALARMCTRL: RTC_ALARM pin output control */ +#define CREG_CREG0_ALARMCTRL_SHIFT (6) +#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT) +#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT) + +/* BODLVL1: BOD trip level to generate an interrupt */ +#define CREG_CREG0_BODLVL1_SHIFT (8) +#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT) +#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT) + +/* BODLVL2: BOD trip level to generate a reset */ +#define CREG_CREG0_BODLVL2_SHIFT (10) +#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT) +#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT) + +/* SAMPLECTRL: SAMPLE pin input/output control */ +#define CREG_CREG0_SAMPLECTRL_SHIFT (12) +#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT) +#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT) + +/* WAKEUP0CTRL: WAKEUP0 pin input/output control */ +#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14) +#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT) +#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT) + +/* WAKEUP1CTRL: WAKEUP1 pin input/output control */ +#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16) +#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT) +#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT) + +/* --- CREG_M4MEMMAP values ------------------------------------- */ + +/* M4MAP: Shadow address when accessing memory at address 0x00000000 */ +#define CREG_M4MEMMAP_M4MAP_SHIFT (12) +#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT) +#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT) + +/* --- CREG_CREG5 values ---------------------------------------- */ + +/* M4TAPSEL: JTAG debug select for M4 core */ +#define CREG_CREG5_M4TAPSEL_SHIFT (6) +#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT) + +/* M0APPTAPSEL: JTAG debug select for M0 co-processor */ +#define CREG_CREG5_M0APPTAPSEL_SHIFT (9) +#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT) + +/* --- CREG_DMAMUX values --------------------------------------- */ + +/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */ +#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0) +#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT) +#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT) + +/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */ +#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2) +#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT) +#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT) + +/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */ +#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4) +#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT) +#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT) + +/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */ +#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6) +#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT) +#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT) + +/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */ +#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8) +#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT) +#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT) + +/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */ +#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10) +#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT) +#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT) + +/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */ +#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12) +#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT) +#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT) + +/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */ +#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14) +#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT) +#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT) + +/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */ +#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16) +#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT) +#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT) + +/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */ +#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18) +#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT) +#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT) + +/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */ +#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20) +#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT) +#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT) + +/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */ +#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22) +#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT) +#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT) + +/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */ +#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24) +#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT) +#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT) + +/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */ +#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26) +#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT) +#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT) + +/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */ +#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28) +#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT) +#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT) + +/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */ +#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30) +#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT) +#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT) + +/* --- CREG_FLASHCFGA values ------------------------------------ */ + +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access */ +#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12) +#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT) +#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT) + +/* POW: Flash bank A power control */ +#define CREG_FLASHCFGA_POW_SHIFT (31) +#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT) + +/* --- CREG_FLASHCFGB values ------------------------------------ */ + +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access */ +#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12) +#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT) +#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT) + +/* POW: Flash bank B power control */ +#define CREG_FLASHCFGB_POW_SHIFT (31) +#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT) + +/* --- CREG_ETBCFG values --------------------------------------- */ + +/* ETB: Select SRAM interface */ +#define CREG_ETBCFG_ETB_SHIFT (0) +#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT) + +/* --- CREG_CREG6 values ---------------------------------------- */ + +/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the PHY interface */ +#define CREG_CREG6_ETHMODE_SHIFT (0) +#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT) +#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT) + +/* CTOUTCTRL: Selects the functionality of the SCT outputs */ +#define CREG_CREG6_CTOUTCTRL_SHIFT (4) +#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT) + +/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */ +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12) +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT) + +/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */ +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13) +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT) + +/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */ +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14) +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT) + +/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */ +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15) +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT) + +/* EMC_CLK_SEL: EMC_CLK divided clock select */ +#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16) +#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT) + +/* --- CREG_M4TXEVENT values ------------------------------------ */ + +/* TXEVCLR: Cortex-M4 TXEV event */ +#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0) +#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT) + +/* --- CREG_M0TXEVENT values ------------------------------------ */ + +/* TXEVCLR: Cortex-M0 TXEV event */ +#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0) +#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT) + +/* --- CREG_M0APPMEMMAP values ---------------------------------- */ + +/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */ +#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12) +#define CREG_M0APPMEMMAP_M0APPMAP_MASK (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) +#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) + +/* --- CREG_USB0FLADJ values ------------------------------------ */ + +/* FLTV: Frame length timing value */ +#define CREG_USB0FLADJ_FLTV_SHIFT (0) +#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT) +#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT) + +/* --- CREG_USB1FLADJ values ------------------------------------ */ + +/* FLTV: Frame length timing value */ +#define CREG_USB1FLADJ_FLTV_SHIFT (0) +#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT) +#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT) + /**@}*/ #endif diff --git a/include/libopencm3/lpc43xx/rgu.h b/include/libopencm3/lpc43xx/rgu.h index 4952ec1b..09338c8c 100644 --- a/include/libopencm3/lpc43xx/rgu.h +++ b/include/libopencm3/lpc43xx/rgu.h @@ -257,6 +257,885 @@ LGPL License Terms @ref lgpl_license /* Reserved */ #define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC) +/* --- RESET_CTRL0 values --------------------------------------- */ + +/* CORE_RST: Writing a one activates the reset */ +#define RESET_CTRL0_CORE_RST_SHIFT (0) +#define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT) + +/* PERIPH_RST: Writing a one activates the reset */ +#define RESET_CTRL0_PERIPH_RST_SHIFT (1) +#define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Writing a one activates the reset */ +#define RESET_CTRL0_MASTER_RST_SHIFT (2) +#define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT) + +/* WWDT_RST: Writing a one to this bit has no effect */ +#define RESET_CTRL0_WWDT_RST_SHIFT (4) +#define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT) + +/* CREG_RST: Writing a one to this bit has no effect */ +#define RESET_CTRL0_CREG_RST_SHIFT (5) +#define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT) + +/* BUS_RST: Writing a one activates the reset */ +#define RESET_CTRL0_BUS_RST_SHIFT (8) +#define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT) + +/* SCU_RST: Writing a one activates the reset */ +#define RESET_CTRL0_SCU_RST_SHIFT (9) +#define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT) + +/* M4_RST: Writing a one activates the reset */ +#define RESET_CTRL0_M4_RST_SHIFT (13) +#define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT) + +/* LCD_RST: Writing a one activates the reset */ +#define RESET_CTRL0_LCD_RST_SHIFT (16) +#define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT) + +/* USB0_RST: Writing a one activates the reset */ +#define RESET_CTRL0_USB0_RST_SHIFT (17) +#define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT) + +/* USB1_RST: Writing a one activates the reset */ +#define RESET_CTRL0_USB1_RST_SHIFT (18) +#define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT) + +/* DMA_RST: Writing a one activates the reset */ +#define RESET_CTRL0_DMA_RST_SHIFT (19) +#define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT) + +/* SDIO_RST: Writing a one activates the reset */ +#define RESET_CTRL0_SDIO_RST_SHIFT (20) +#define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT) + +/* EMC_RST: Writing a one activates the reset */ +#define RESET_CTRL0_EMC_RST_SHIFT (21) +#define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT) + +/* ETHERNET_RST: Writing a one activates the reset */ +#define RESET_CTRL0_ETHERNET_RST_SHIFT (22) +#define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Writing a one activates the reset */ +#define RESET_CTRL0_FLASHA_RST_SHIFT (25) +#define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Writing a one activates the reset */ +#define RESET_CTRL0_EEPROM_RST_SHIFT (27) +#define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT) + +/* GPIO_RST: Writing a one activates the reset */ +#define RESET_CTRL0_GPIO_RST_SHIFT (28) +#define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT) + +/* FLASHB_RST: Writing a one activates the reset */ +#define RESET_CTRL0_FLASHB_RST_SHIFT (29) +#define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT) + +/* --- RESET_CTRL1 values --------------------------------------- */ + +/* TIMER0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER0_RST_SHIFT (0) +#define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER1_RST_SHIFT (1) +#define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER2_RST_SHIFT (2) +#define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER3_RST_SHIFT (3) +#define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT) + +/* RTIMER_RST: Writing a one activates the reset */ +#define RESET_CTRL1_RTIMER_RST_SHIFT (4) +#define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT) + +/* SCT_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SCT_RST_SHIFT (5) +#define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Writing a one activates the reset */ +#define RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6) +#define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_QEI_RST_SHIFT (7) +#define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT) + +/* ADC0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_ADC0_RST_SHIFT (8) +#define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT) + +/* ADC1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_ADC1_RST_SHIFT (9) +#define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT) + +/* DAC_RST: Writing a one activates the reset */ +#define RESET_CTRL1_DAC_RST_SHIFT (10) +#define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT) + +/* UART0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART0_RST_SHIFT (12) +#define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT) + +/* UART1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART1_RST_SHIFT (13) +#define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT) + +/* UART2_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART2_RST_SHIFT (14) +#define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT) + +/* UART3_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART3_RST_SHIFT (15) +#define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT) + +/* I2C0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2C0_RST_SHIFT (16) +#define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT) + +/* I2C1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2C1_RST_SHIFT (17) +#define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT) + +/* SSP0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SSP0_RST_SHIFT (18) +#define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT) + +/* SSP1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SSP1_RST_SHIFT (19) +#define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT) + +/* I2S_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2S_RST_SHIFT (20) +#define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT) + +/* SPIFI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SPIFI_RST_SHIFT (21) +#define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT) + +/* CAN1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_CAN1_RST_SHIFT (22) +#define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT) + +/* CAN0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_CAN0_RST_SHIFT (23) +#define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT) + +/* M0APP_RST: Writing a one activates the reset */ +#define RESET_CTRL1_M0APP_RST_SHIFT (24) +#define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT) + +/* SGPIO_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SGPIO_RST_SHIFT (25) +#define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT) + +/* SPI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SPI_RST_SHIFT (26) +#define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT) + +/* --- RESET_STATUS0 values ------------------------------------- */ + +/* CORE_RST: Status of the CORE_RST reset generator output */ +#define RESET_STATUS0_CORE_RST_SHIFT (0) +#define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT) +#define RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT) + +/* PERIPH_RST: Status of the PERIPH_RST reset generator output */ +#define RESET_STATUS0_PERIPH_RST_SHIFT (2) +#define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT) +#define RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Status of the MASTER_RST reset generator output */ +#define RESET_STATUS0_MASTER_RST_SHIFT (4) +#define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT) +#define RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT) + +/* WWDT_RST: Status of the WWDT_RST reset generator output */ +#define RESET_STATUS0_WWDT_RST_SHIFT (8) +#define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT) +#define RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT) + +/* CREG_RST: Status of the CREG_RST reset generator output */ +#define RESET_STATUS0_CREG_RST_SHIFT (10) +#define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT) +#define RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT) + +/* BUS_RST: Status of the BUS_RST reset generator output */ +#define RESET_STATUS0_BUS_RST_SHIFT (16) +#define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT) +#define RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT) + +/* SCU_RST: Status of the SCU_RST reset generator output */ +#define RESET_STATUS0_SCU_RST_SHIFT (18) +#define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT) +#define RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT) + +/* M4_RST: Status of the M4_RST reset generator output */ +#define RESET_STATUS0_M4_RST_SHIFT (26) +#define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT) +#define RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT) + +/* --- RESET_STATUS1 values ------------------------------------- */ + +/* LCD_RST: Status of the LCD_RST reset generator output */ +#define RESET_STATUS1_LCD_RST_SHIFT (0) +#define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT) +#define RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT) + +/* USB0_RST: Status of the USB0_RST reset generator output */ +#define RESET_STATUS1_USB0_RST_SHIFT (2) +#define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT) +#define RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT) + +/* USB1_RST: Status of the USB1_RST reset generator output */ +#define RESET_STATUS1_USB1_RST_SHIFT (4) +#define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT) +#define RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT) + +/* DMA_RST: Status of the DMA_RST reset generator output */ +#define RESET_STATUS1_DMA_RST_SHIFT (6) +#define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT) +#define RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT) + +/* SDIO_RST: Status of the SDIO_RST reset generator output */ +#define RESET_STATUS1_SDIO_RST_SHIFT (8) +#define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT) +#define RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT) + +/* EMC_RST: Status of the EMC_RST reset generator output */ +#define RESET_STATUS1_EMC_RST_SHIFT (10) +#define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT) +#define RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT) + +/* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */ +#define RESET_STATUS1_ETHERNET_RST_SHIFT (12) +#define RESET_STATUS1_ETHERNET_RST_MASK (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) +#define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Status of the FLASHA_RST reset generator output */ +#define RESET_STATUS1_FLASHA_RST_SHIFT (18) +#define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT) +#define RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Status of the EEPROM_RST reset generator output */ +#define RESET_STATUS1_EEPROM_RST_SHIFT (22) +#define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT) +#define RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT) + +/* GPIO_RST: Status of the GPIO_RST reset generator output */ +#define RESET_STATUS1_GPIO_RST_SHIFT (24) +#define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT) +#define RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT) + +/* FLASHB_RST: Status of the FLASHB_RST reset generator output */ +#define RESET_STATUS1_FLASHB_RST_SHIFT (26) +#define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT) +#define RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT) + +/* --- RESET_STATUS2 values ------------------------------------- */ + +/* TIMER0_RST: Status of the TIMER0_RST reset generator output */ +#define RESET_STATUS2_TIMER0_RST_SHIFT (0) +#define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT) +#define RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Status of the TIMER1_RST reset generator output */ +#define RESET_STATUS2_TIMER1_RST_SHIFT (2) +#define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT) +#define RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Status of the TIMER2_RST reset generator output */ +#define RESET_STATUS2_TIMER2_RST_SHIFT (4) +#define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT) +#define RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Status of the TIMER3_RST reset generator output */ +#define RESET_STATUS2_TIMER3_RST_SHIFT (6) +#define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT) +#define RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT) + +/* RITIMER_RST: Status of the RITIMER_RST reset generator output */ +#define RESET_STATUS2_RITIMER_RST_SHIFT (8) +#define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT) +#define RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT) + +/* SCT_RST: Status of the SCT_RST reset generator output */ +#define RESET_STATUS2_SCT_RST_SHIFT (10) +#define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT) +#define RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */ +#define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12) +#define RESET_STATUS2_MOTOCONPWM_RST_MASK (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) +#define RESET_STATUS2_MOTOCONPWM_RST(x) ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Status of the QEI_RST reset generator output */ +#define RESET_STATUS2_QEI_RST_SHIFT (14) +#define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT) +#define RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT) + +/* ADC0_RST: Status of the ADC0_RST reset generator output */ +#define RESET_STATUS2_ADC0_RST_SHIFT (16) +#define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT) +#define RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT) + +/* ADC1_RST: Status of the ADC1_RST reset generator output */ +#define RESET_STATUS2_ADC1_RST_SHIFT (18) +#define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT) +#define RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT) + +/* DAC_RST: Status of the DAC_RST reset generator output */ +#define RESET_STATUS2_DAC_RST_SHIFT (20) +#define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT) +#define RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT) + +/* UART0_RST: Status of the UART0_RST reset generator output */ +#define RESET_STATUS2_UART0_RST_SHIFT (24) +#define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT) +#define RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT) + +/* UART1_RST: Status of the UART1_RST reset generator output */ +#define RESET_STATUS2_UART1_RST_SHIFT (26) +#define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT) +#define RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT) + +/* UART2_RST: Status of the UART2_RST reset generator output */ +#define RESET_STATUS2_UART2_RST_SHIFT (28) +#define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT) +#define RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT) + +/* UART3_RST: Status of the UART3_RST reset generator output */ +#define RESET_STATUS2_UART3_RST_SHIFT (30) +#define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT) +#define RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT) + +/* --- RESET_STATUS3 values ------------------------------------- */ + +/* I2C0_RST: Status of the I2C0_RST reset generator output */ +#define RESET_STATUS3_I2C0_RST_SHIFT (0) +#define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT) +#define RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT) + +/* I2C1_RST: Status of the I2C1_RST reset generator output */ +#define RESET_STATUS3_I2C1_RST_SHIFT (2) +#define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT) +#define RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT) + +/* SSP0_RST: Status of the SSP0_RST reset generator output */ +#define RESET_STATUS3_SSP0_RST_SHIFT (4) +#define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT) +#define RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT) + +/* SSP1_RST: Status of the SSP1_RST reset generator output */ +#define RESET_STATUS3_SSP1_RST_SHIFT (6) +#define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT) +#define RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT) + +/* I2S_RST: Status of the I2S_RST reset generator output */ +#define RESET_STATUS3_I2S_RST_SHIFT (8) +#define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT) +#define RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT) + +/* SPIFI_RST: Status of the SPIFI_RST reset generator output */ +#define RESET_STATUS3_SPIFI_RST_SHIFT (10) +#define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT) +#define RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT) + +/* CAN1_RST: Status of the CAN1_RST reset generator output */ +#define RESET_STATUS3_CAN1_RST_SHIFT (12) +#define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT) +#define RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT) + +/* CAN0_RST: Status of the CAN0_RST reset generator output */ +#define RESET_STATUS3_CAN0_RST_SHIFT (14) +#define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT) +#define RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT) + +/* M0APP_RST: Status of the M0APP_RST reset generator output */ +#define RESET_STATUS3_M0APP_RST_SHIFT (16) +#define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT) +#define RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT) + +/* SGPIO_RST: Status of the SGPIO_RST reset generator output */ +#define RESET_STATUS3_SGPIO_RST_SHIFT (18) +#define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT) +#define RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT) + +/* SPI_RST: Status of the SPI_RST reset generator output */ +#define RESET_STATUS3_SPI_RST_SHIFT (20) +#define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT) +#define RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT) + +/* --- RESET_ACTIVE_STATUS0 values ------------------------------ */ + +/* CORE_RST: Current status of the CORE_RST */ +#define RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0) +#define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT) + +/* PERIPH_RST: Current status of the PERIPH_RST */ +#define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1) +#define RESET_ACTIVE_STATUS0_PERIPH_RST (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Current status of the MASTER_RST */ +#define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2) +#define RESET_ACTIVE_STATUS0_MASTER_RST (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) + +/* WWDT_RST: Current status of the WWDT_RST */ +#define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4) +#define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT) + +/* CREG_RST: Current status of the CREG_RST */ +#define RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5) +#define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT) + +/* BUS_RST: Current status of the BUS_RST */ +#define RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8) +#define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT) + +/* SCU_RST: Current status of the SCU_RST */ +#define RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9) +#define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT) + +/* M4_RST: Current status of the M4_RST */ +#define RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13) +#define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT) + +/* LCD_RST: Current status of the LCD_RST */ +#define RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16) +#define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT) + +/* USB0_RST: Current status of the USB0_RST */ +#define RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17) +#define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT) + +/* USB1_RST: Current status of the USB1_RST */ +#define RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18) +#define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT) + +/* DMA_RST: Current status of the DMA_RST */ +#define RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19) +#define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT) + +/* SDIO_RST: Current status of the SDIO_RST */ +#define RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20) +#define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT) + +/* EMC_RST: Current status of the EMC_RST */ +#define RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21) +#define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT) + +/* ETHERNET_RST: Current status of the ETHERNET_RST */ +#define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22) +#define RESET_ACTIVE_STATUS0_ETHERNET_RST (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Current status of the FLASHA_RST */ +#define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25) +#define RESET_ACTIVE_STATUS0_FLASHA_RST (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Current status of the EEPROM_RST */ +#define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27) +#define RESET_ACTIVE_STATUS0_EEPROM_RST (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) + +/* GPIO_RST: Current status of the GPIO_RST */ +#define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28) +#define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT) + +/* FLASHB_RST: Current status of the FLASHB_RST */ +#define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29) +#define RESET_ACTIVE_STATUS0_FLASHB_RST (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) + +/* --- RESET_ACTIVE_STATUS1 values ------------------------------ */ + +/* TIMER0_RST: Current status of the TIMER0_RST */ +#define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0) +#define RESET_ACTIVE_STATUS1_TIMER0_RST (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Current status of the TIMER1_RST */ +#define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1) +#define RESET_ACTIVE_STATUS1_TIMER1_RST (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Current status of the TIMER2_RST */ +#define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2) +#define RESET_ACTIVE_STATUS1_TIMER2_RST (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Current status of the TIMER3_RST */ +#define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3) +#define RESET_ACTIVE_STATUS1_TIMER3_RST (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) + +/* RITIMER_RST: Current status of the RITIMER_RST */ +#define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4) +#define RESET_ACTIVE_STATUS1_RITIMER_RST (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) + +/* SCT_RST: Current status of the SCT_RST */ +#define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5) +#define RESET_ACTIVE_STATUS1_SCT_RST (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */ +#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6) +#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Current status of the QEI_RST */ +#define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7) +#define RESET_ACTIVE_STATUS1_QEI_RST (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) + +/* ADC0_RST: Current status of the ADC0_RST */ +#define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8) +#define RESET_ACTIVE_STATUS1_ADC0_RST (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) + +/* ADC1_RST: Current status of the ADC1_RST */ +#define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9) +#define RESET_ACTIVE_STATUS1_ADC1_RST (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) + +/* DAC_RST: Current status of the DAC_RST */ +#define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10) +#define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT) + +/* UART0_RST: Current status of the UART0_RST */ +#define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12) +#define RESET_ACTIVE_STATUS1_UART0_RST (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) + +/* UART1_RST: Current status of the UART1_RST */ +#define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13) +#define RESET_ACTIVE_STATUS1_UART1_RST (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) + +/* UART2_RST: Current status of the UART2_RST */ +#define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14) +#define RESET_ACTIVE_STATUS1_UART2_RST (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) + +/* UART3_RST: Current status of the UART3_RST */ +#define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15) +#define RESET_ACTIVE_STATUS1_UART3_RST (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) + +/* I2C0_RST: Current status of the I2C0_RST */ +#define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16) +#define RESET_ACTIVE_STATUS1_I2C0_RST (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) + +/* I2C1_RST: Current status of the I2C1_RST */ +#define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17) +#define RESET_ACTIVE_STATUS1_I2C1_RST (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) + +/* SSP0_RST: Current status of the SSP0_RST */ +#define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18) +#define RESET_ACTIVE_STATUS1_SSP0_RST (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) + +/* SSP1_RST: Current status of the SSP1_RST */ +#define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19) +#define RESET_ACTIVE_STATUS1_SSP1_RST (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) + +/* I2S_RST: Current status of the I2S_RST */ +#define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20) +#define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT) + +/* SPIFI_RST: Current status of the SPIFI_RST */ +#define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21) +#define RESET_ACTIVE_STATUS1_SPIFI_RST (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) + +/* CAN1_RST: Current status of the CAN1_RST */ +#define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22) +#define RESET_ACTIVE_STATUS1_CAN1_RST (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) + +/* CAN0_RST: Current status of the CAN0_RST */ +#define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23) +#define RESET_ACTIVE_STATUS1_CAN0_RST (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) + +/* M0APP_RST: Current status of the M0APP_RST */ +#define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24) +#define RESET_ACTIVE_STATUS1_M0APP_RST (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) + +/* SGPIO_RST: Current status of the SGPIO_RST */ +#define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25) +#define RESET_ACTIVE_STATUS1_SGPIO_RST (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) + +/* SPI_RST: Current status of the SPI_RST */ +#define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26) +#define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT) + +/* --- RESET_EXT_STAT0 values ----------------------------------- */ + +/* EXT_RESET: Reset activated by external reset from reset pin */ +#define RESET_EXT_STAT0_EXT_RESET_SHIFT (0) +#define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT) + +/* BOD_RESET: Reset activated by BOD reset */ +#define RESET_EXT_STAT0_BOD_RESET_SHIFT (4) +#define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT) + +/* WWDT_RESET: Reset activated by WWDT time-out */ +#define RESET_EXT_STAT0_WWDT_RESET_SHIFT (5) +#define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT) + +/* --- RESET_EXT_STAT1 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT1_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT2 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT2_PERIPHERAL_RESET (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT4 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT4_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT5 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT5_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT8 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT8_PERIPHERAL_RESET (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT9 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT9_PERIPHERAL_RESET (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT13 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT13_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT16 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT16_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT17 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT17_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT18 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT18_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT19 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT19_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT20 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT20_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT21 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT21_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT22 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT22_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT25 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT25_PERIPHERAL_RESET (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT27 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT27_PERIPHERAL_RESET (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT28 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT28_PERIPHERAL_RESET (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT29 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT29_PERIPHERAL_RESET (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT32 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT32_PERIPHERAL_RESET (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT33 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT33_PERIPHERAL_RESET (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT34 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT34_PERIPHERAL_RESET (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT35 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT35_PERIPHERAL_RESET (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT36 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT36_PERIPHERAL_RESET (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT37 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT37_PERIPHERAL_RESET (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT38 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT38_PERIPHERAL_RESET (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT39 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT39_PERIPHERAL_RESET (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT40 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT40_PERIPHERAL_RESET (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT41 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT41_PERIPHERAL_RESET (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT42 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT42_PERIPHERAL_RESET (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT44 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT44_PERIPHERAL_RESET (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT45 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT45_PERIPHERAL_RESET (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT46 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT46_PERIPHERAL_RESET (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT47 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT47_PERIPHERAL_RESET (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT48 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT48_PERIPHERAL_RESET (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT49 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT49_PERIPHERAL_RESET (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT50 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT50_PERIPHERAL_RESET (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT51 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT51_PERIPHERAL_RESET (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT52 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT52_PERIPHERAL_RESET (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT53 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT53_PERIPHERAL_RESET (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT54 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT54_PERIPHERAL_RESET (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT55 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT55_PERIPHERAL_RESET (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT56 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT56_PERIPHERAL_RESET (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT57 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT57_PERIPHERAL_RESET (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT58 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT58_PERIPHERAL_RESET (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) + /**@}*/ #endif diff --git a/include/libopencm3/lpc43xx/usb.h b/include/libopencm3/lpc43xx/usb.h index 7c832a02..6409a95c 100644 --- a/include/libopencm3/lpc43xx/usb.h +++ b/include/libopencm3/lpc43xx/usb.h @@ -149,7 +149,1027 @@ /* Endpoint control 5 */ #define USB0_ENDPTCTRL5 MMIO32(USB0_BASE + 0x1D4) +/* --- USB0_CAPLENGTH values ------------------------------------ */ +/* CAPLENGTH: Indicates offset to add to the register base address at the beginning of the Operational Register */ +#define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0) +#define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT) +#define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT) + +/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host controller */ +#define USB0_CAPLENGTH_HCIVERSION_SHIFT (8) +#define USB0_CAPLENGTH_HCIVERSION_MASK (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) +#define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT) + +/* --- USB0_HCSPARAMS values ------------------------------------ */ + +/* N_PORTS: Number of downstream ports */ +#define USB0_HCSPARAMS_N_PORTS_SHIFT (0) +#define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT) +#define USB0_HCSPARAMS_N_PORTS(x) ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT) + +/* PPC: Port Power Control */ +#define USB0_HCSPARAMS_PPC_SHIFT (4) +#define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT) + +/* N_PCC: Number of Ports per Companion Controller */ +#define USB0_HCSPARAMS_N_PCC_SHIFT (8) +#define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT) +#define USB0_HCSPARAMS_N_PCC(x) ((x) << USB0_HCSPARAMS_N_PCC_SHIFT) + +/* N_CC: Number of Companion Controller */ +#define USB0_HCSPARAMS_N_CC_SHIFT (12) +#define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT) +#define USB0_HCSPARAMS_N_CC(x) ((x) << USB0_HCSPARAMS_N_CC_SHIFT) + +/* PI: Port indicators */ +#define USB0_HCSPARAMS_PI_SHIFT (16) +#define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT) + +/* N_PTT: Number of Ports per Transaction Translator */ +#define USB0_HCSPARAMS_N_PTT_SHIFT (20) +#define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT) +#define USB0_HCSPARAMS_N_PTT(x) ((x) << USB0_HCSPARAMS_N_PTT_SHIFT) + +/* N_TT: Number of Transaction Translators */ +#define USB0_HCSPARAMS_N_TT_SHIFT (24) +#define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT) +#define USB0_HCSPARAMS_N_TT(x) ((x) << USB0_HCSPARAMS_N_TT_SHIFT) + +/* --- USB0_HCCPARAMS values ------------------------------------ */ + +/* ADC: 64-bit Addressing Capability */ +#define USB0_HCCPARAMS_ADC_SHIFT (0) +#define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT) + +/* PFL: Programmable Frame List Flag */ +#define USB0_HCCPARAMS_PFL_SHIFT (1) +#define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT) + +/* ASP: Asynchronous Schedule Park Capability */ +#define USB0_HCCPARAMS_ASP_SHIFT (2) +#define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT) + +/* IST: Isochronous Scheduling Threshold */ +#define USB0_HCCPARAMS_IST_SHIFT (4) +#define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT) +#define USB0_HCCPARAMS_IST(x) ((x) << USB0_HCCPARAMS_IST_SHIFT) + +/* EECP: EHCI Extended Capabilities Pointer */ +#define USB0_HCCPARAMS_EECP_SHIFT (8) +#define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT) +#define USB0_HCCPARAMS_EECP(x) ((x) << USB0_HCCPARAMS_EECP_SHIFT) + +/* --- USB0_DCCPARAMS values ------------------------------------ */ + +/* DEN: Device Endpoint Number */ +#define USB0_DCCPARAMS_DEN_SHIFT (0) +#define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT) +#define USB0_DCCPARAMS_DEN(x) ((x) << USB0_DCCPARAMS_DEN_SHIFT) + +/* DC: Device Capable */ +#define USB0_DCCPARAMS_DC_SHIFT (7) +#define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT) + +/* HC: Host Capable */ +#define USB0_DCCPARAMS_HC_SHIFT (8) +#define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT) + +/* --- USB0_USBCMD_D values ------------------------------------- */ + +/* RS: Run/Stop */ +#define USB0_USBCMD_D_RS_SHIFT (0) +#define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT) + +/* RST: Controller reset */ +#define USB0_USBCMD_D_RST_SHIFT (1) +#define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT) + +/* SUTW: Setup trip wire */ +#define USB0_USBCMD_D_SUTW_SHIFT (13) +#define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT) + +/* ATDTW: Add dTD trip wire */ +#define USB0_USBCMD_D_ATDTW_SHIFT (14) +#define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT) + +/* ITC: Interrupt threshold control */ +#define USB0_USBCMD_D_ITC_SHIFT (16) +#define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT) +#define USB0_USBCMD_D_ITC(x) ((x) << USB0_USBCMD_D_ITC_SHIFT) + +/* --- USB0_USBCMD_H values ------------------------------------- */ + +/* RS: Run/Stop */ +#define USB0_USBCMD_H_RS_SHIFT (0) +#define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT) + +/* RST: Controller reset */ +#define USB0_USBCMD_H_RST_SHIFT (1) +#define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT) + +/* FS0: Bit 0 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS0_SHIFT (2) +#define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT) + +/* FS1: Bit 1 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS1_SHIFT (3) +#define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT) + +/* PSE: This bit controls whether the host controller skips processing the periodic schedule */ +#define USB0_USBCMD_H_PSE_SHIFT (4) +#define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT) + +/* ASE: This bit controls whether the host controller skips processing the asynchronous schedule */ +#define USB0_USBCMD_H_ASE_SHIFT (5) +#define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT) + +/* IAA: This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule */ +#define USB0_USBCMD_H_IAA_SHIFT (6) +#define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT) + +/* ASP1_0: Asynchronous schedule park mode */ +#define USB0_USBCMD_H_ASP1_0_SHIFT (8) +#define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT) +#define USB0_USBCMD_H_ASP1_0(x) ((x) << USB0_USBCMD_H_ASP1_0_SHIFT) + +/* ASPE: Asynchronous Schedule Park Mode Enable */ +#define USB0_USBCMD_H_ASPE_SHIFT (11) +#define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT) + +/* FS2: Bit 2 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS2_SHIFT (15) +#define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT) + +/* ITC: Interrupt threshold control */ +#define USB0_USBCMD_H_ITC_SHIFT (16) +#define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT) +#define USB0_USBCMD_H_ITC(x) ((x) << USB0_USBCMD_H_ITC_SHIFT) + +/* --- USB0_USBSTS_D values ------------------------------------- */ + +/* UI: USB interrupt */ +#define USB0_USBSTS_D_UI_SHIFT (0) +#define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT) + +/* UEI: USB error interrupt */ +#define USB0_USBSTS_D_UEI_SHIFT (1) +#define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT) + +/* PCI: Port change detect */ +#define USB0_USBSTS_D_PCI_SHIFT (2) +#define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT) + +/* URI: USB reset received */ +#define USB0_USBSTS_D_URI_SHIFT (6) +#define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT) + +/* SRI: SOF received */ +#define USB0_USBSTS_D_SRI_SHIFT (7) +#define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT) + +/* SLI: DCSuspend */ +#define USB0_USBSTS_D_SLI_SHIFT (8) +#define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT) + +/* NAKI: NAK interrupt bit */ +#define USB0_USBSTS_D_NAKI_SHIFT (16) +#define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT) + +/* --- USB0_USBSTS_H values ------------------------------------- */ + +/* UI: USB interrupt */ +#define USB0_USBSTS_H_UI_SHIFT (0) +#define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT) + +/* UEI: USB error interrupt */ +#define USB0_USBSTS_H_UEI_SHIFT (1) +#define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT) + +/* PCI: Port change detect */ +#define USB0_USBSTS_H_PCI_SHIFT (2) +#define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT) + +/* FRI: Frame list roll-over */ +#define USB0_USBSTS_H_FRI_SHIFT (3) +#define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT) + +/* AAI: Interrupt on async advance */ +#define USB0_USBSTS_H_AAI_SHIFT (5) +#define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT) + +/* SRI: SOF received */ +#define USB0_USBSTS_H_SRI_SHIFT (7) +#define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT) + +/* HCH: HCHalted */ +#define USB0_USBSTS_H_HCH_SHIFT (12) +#define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT) + +/* RCL: Reclamation */ +#define USB0_USBSTS_H_RCL_SHIFT (13) +#define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT) + +/* PS: Periodic schedule status */ +#define USB0_USBSTS_H_PS_SHIFT (14) +#define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT) + +/* AS: Asynchronous schedule status */ +#define USB0_USBSTS_H_AS_SHIFT (15) +#define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT) + +/* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */ +#define USB0_USBSTS_H_UAI_SHIFT (18) +#define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT) + +/* UPI: USB host periodic interrupt (USBHSTPERINT) */ +#define USB0_USBSTS_H_UPI_SHIFT (19) +#define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT) + +/* --- USB0_USBINTR_D values ------------------------------------ */ + +/* UE: USB interrupt enable */ +#define USB0_USBINTR_D_UE_SHIFT (0) +#define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT) + +/* UEE: USB error interrupt enable */ +#define USB0_USBINTR_D_UEE_SHIFT (1) +#define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT) + +/* PCE: Port change detect enable */ +#define USB0_USBINTR_D_PCE_SHIFT (2) +#define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT) + +/* URE: USB reset enable */ +#define USB0_USBINTR_D_URE_SHIFT (6) +#define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT) + +/* SRE: SOF received enable */ +#define USB0_USBINTR_D_SRE_SHIFT (7) +#define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT) + +/* SLE: Sleep enable */ +#define USB0_USBINTR_D_SLE_SHIFT (8) +#define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT) + +/* NAKE: NAK interrupt enable */ +#define USB0_USBINTR_D_NAKE_SHIFT (16) +#define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT) + +/* --- USB0_USBINTR_H values ------------------------------------ */ + +/* UE: USB interrupt enable */ +#define USB0_USBINTR_H_UE_SHIFT (0) +#define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT) + +/* UEE: USB error interrupt enable */ +#define USB0_USBINTR_H_UEE_SHIFT (1) +#define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT) + +/* PCE: Port change detect enable */ +#define USB0_USBINTR_H_PCE_SHIFT (2) +#define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT) + +/* FRE: Frame list rollover enable */ +#define USB0_USBINTR_H_FRE_SHIFT (3) +#define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT) + +/* AAE: Interrupt on asynchronous advance enable */ +#define USB0_USBINTR_H_AAE_SHIFT (5) +#define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT) + +/* SRE: SOF received enable */ +#define USB0_USBINTR_H_SRE_SHIFT (7) +#define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT) + +/* UAIE: USB host asynchronous interrupt enable */ +#define USB0_USBINTR_H_UAIE_SHIFT (18) +#define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT) + +/* UPIA: USB host periodic interrupt enable */ +#define USB0_USBINTR_H_UPIA_SHIFT (19) +#define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT) + +/* --- USB0_FRINDEX_D values ------------------------------------ */ + +/* FRINDEX2_0: Current micro frame number */ +#define USB0_FRINDEX_D_FRINDEX2_0_SHIFT (0) +#define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) +#define USB0_FRINDEX_D_FRINDEX2_0(x) ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) + +/* FRINDEX13_3: Current frame number of the last frame transmitted */ +#define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3) +#define USB0_FRINDEX_D_FRINDEX13_3_MASK (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) +#define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) + +/* --- USB0_FRINDEX_H values ------------------------------------ */ + +/* FRINDEX2_0: Current micro frame number */ +#define USB0_FRINDEX_H_FRINDEX2_0_SHIFT (0) +#define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) +#define USB0_FRINDEX_H_FRINDEX2_0(x) ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) + +/* FRINDEX12_3: Frame list current index */ +#define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3) +#define USB0_FRINDEX_H_FRINDEX12_3_MASK (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) +#define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) + +/* --- USB0_DEVICEADDR values ----------------------------------- */ + +/* USBADRA: Device address advance */ +#define USB0_DEVICEADDR_USBADRA_SHIFT (24) +#define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT) + +/* USBADR: USB device address */ +#define USB0_DEVICEADDR_USBADR_SHIFT (25) +#define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT) +#define USB0_DEVICEADDR_USBADR(x) ((x) << USB0_DEVICEADDR_USBADR_SHIFT) + +/* --- USB0_PERIODICLISTBASE values ----------------------------- */ + +/* PERBASE31_12: Base Address (Low) */ +#define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12) +#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) +#define USB0_PERIODICLISTBASE_PERBASE31_12(x) ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) + +/* --- USB0_ENDPOINTLISTADDR values ----------------------------- */ + +/* EPBASE31_11: Endpoint list pointer (low) */ +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) + +/* --- USB0_ASYNCLISTADDR values -------------------------------- */ + +/* ASYBASE31_5: Link pointer (Low) LPL */ +#define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5) +#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) +#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) + +/* --- USB0_TTCTRL values --------------------------------------- */ + +/* TTHA: Hub address when FS or LS device are connected directly */ +#define USB0_TTCTRL_TTHA_SHIFT (24) +#define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT) +#define USB0_TTCTRL_TTHA(x) ((x) << USB0_TTCTRL_TTHA_SHIFT) + +/* --- USB0_BURSTSIZE values ------------------------------------ */ + +/* RXPBURST: Programmable RX burst length */ +#define USB0_BURSTSIZE_RXPBURST_SHIFT (0) +#define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT) +#define USB0_BURSTSIZE_RXPBURST(x) ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT) + +/* TXPBURST: Programmable TX burst length */ +#define USB0_BURSTSIZE_TXPBURST_SHIFT (8) +#define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT) +#define USB0_BURSTSIZE_TXPBURST(x) ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT) + +/* --- USB0_TXFILLTUNING values --------------------------------- */ + +/* TXSCHOH: FIFO burst threshold */ +#define USB0_TXFILLTUNING_TXSCHOH_SHIFT (0) +#define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHOH(x) ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT) + +/* TXSCHEATLTH: Scheduler health counter */ +#define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8) +#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHEATLTH(x) ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) + +/* TXFIFOTHRES: Scheduler overhead */ +#define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) +#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) +#define USB0_TXFILLTUNING_TXFIFOTHRES(x) ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) + +/* --- USB0_BINTERVAL values ------------------------------------ */ + +/* BINT: bInterval value */ +#define USB0_BINTERVAL_BINT_SHIFT (0) +#define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT) +#define USB0_BINTERVAL_BINT(x) ((x) << USB0_BINTERVAL_BINT_SHIFT) + +/* --- USB0_ENDPTNAK values ------------------------------------- */ + +/* EPRN: Rx endpoint NAK */ +#define USB0_ENDPTNAK_EPRN_SHIFT (0) +#define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT) +#define USB0_ENDPTNAK_EPRN(x) ((x) << USB0_ENDPTNAK_EPRN_SHIFT) + +/* EPTN: Tx endpoint NAK */ +#define USB0_ENDPTNAK_EPTN_SHIFT (16) +#define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT) +#define USB0_ENDPTNAK_EPTN(x) ((x) << USB0_ENDPTNAK_EPTN_SHIFT) + +/* --- USB0_ENDPTNAKEN values ----------------------------------- */ + +/* EPRNE: Rx endpoint NAK enable */ +#define USB0_ENDPTNAKEN_EPRNE_SHIFT (0) +#define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT) +#define USB0_ENDPTNAKEN_EPRNE(x) ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT) + +/* EPTNE: Tx endpoint NAK */ +#define USB0_ENDPTNAKEN_EPTNE_SHIFT (16) +#define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT) +#define USB0_ENDPTNAKEN_EPTNE(x) ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT) + +/* --- USB0_PORTSC1_D values ------------------------------------ */ + +/* CCS: Current connect status */ +#define USB0_PORTSC1_D_CCS_SHIFT (0) +#define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT) + +/* PE: Port enable */ +#define USB0_PORTSC1_D_PE_SHIFT (2) +#define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT) + +/* PEC: Port enable/disable change */ +#define USB0_PORTSC1_D_PEC_SHIFT (3) +#define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT) + +/* FPR: Force port resume */ +#define USB0_PORTSC1_D_FPR_SHIFT (6) +#define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT) + +/* SUSP: Suspend */ +#define USB0_PORTSC1_D_SUSP_SHIFT (7) +#define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT) + +/* PR: Port reset */ +#define USB0_PORTSC1_D_PR_SHIFT (8) +#define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT) + +/* HSP: High-speed status */ +#define USB0_PORTSC1_D_HSP_SHIFT (9) +#define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT) + +/* PIC1_0: Port indicator control */ +#define USB0_PORTSC1_D_PIC1_0_SHIFT (14) +#define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT) +#define USB0_PORTSC1_D_PIC1_0(x) ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT) + +/* PTC3_0: Port test control */ +#define USB0_PORTSC1_D_PTC3_0_SHIFT (16) +#define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT) +#define USB0_PORTSC1_D_PTC3_0(x) ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT) + +/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ +#define USB0_PORTSC1_D_PHCD_SHIFT (23) +#define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT) + +/* PFSC: Port force full speed connect */ +#define USB0_PORTSC1_D_PFSC_SHIFT (24) +#define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT) + +/* PSPD: Port speed */ +#define USB0_PORTSC1_D_PSPD_SHIFT (26) +#define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT) +#define USB0_PORTSC1_D_PSPD(x) ((x) << USB0_PORTSC1_D_PSPD_SHIFT) + +/* --- USB0_PORTSC1_H values ------------------------------------ */ + +/* CCS: Current connect status */ +#define USB0_PORTSC1_H_CCS_SHIFT (0) +#define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT) + +/* CSC: Connect status change */ +#define USB0_PORTSC1_H_CSC_SHIFT (1) +#define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT) + +/* PE: Port enable */ +#define USB0_PORTSC1_H_PE_SHIFT (2) +#define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT) + +/* PEC: Port disable/enable change */ +#define USB0_PORTSC1_H_PEC_SHIFT (3) +#define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT) + +/* OCA: Over-current active */ +#define USB0_PORTSC1_H_OCA_SHIFT (4) +#define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT) + +/* OCC: Over-current change */ +#define USB0_PORTSC1_H_OCC_SHIFT (5) +#define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT) + +/* FPR: Force port resume */ +#define USB0_PORTSC1_H_FPR_SHIFT (6) +#define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT) + +/* SUSP: Suspend */ +#define USB0_PORTSC1_H_SUSP_SHIFT (7) +#define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT) + +/* PR: Port reset */ +#define USB0_PORTSC1_H_PR_SHIFT (8) +#define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT) + +/* HSP: High-speed status */ +#define USB0_PORTSC1_H_HSP_SHIFT (9) +#define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT) + +/* LS: Line status */ +#define USB0_PORTSC1_H_LS_SHIFT (10) +#define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT) +#define USB0_PORTSC1_H_LS(x) ((x) << USB0_PORTSC1_H_LS_SHIFT) + +/* PP: Port power control */ +#define USB0_PORTSC1_H_PP_SHIFT (12) +#define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT) + +/* PIC1_0: Port indicator control */ +#define USB0_PORTSC1_H_PIC1_0_SHIFT (14) +#define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT) +#define USB0_PORTSC1_H_PIC1_0(x) ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT) + +/* PTC3_0: Port test control */ +#define USB0_PORTSC1_H_PTC3_0_SHIFT (16) +#define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT) +#define USB0_PORTSC1_H_PTC3_0(x) ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT) + +/* WKCN: Wake on connect enable (WKCNNT_E) */ +#define USB0_PORTSC1_H_WKCN_SHIFT (20) +#define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT) + +/* WKDC: Wake on disconnect enable (WKDSCNNT_E) */ +#define USB0_PORTSC1_H_WKDC_SHIFT (21) +#define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT) + +/* WKOC: Wake on over-current enable (WKOC_E) */ +#define USB0_PORTSC1_H_WKOC_SHIFT (22) +#define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT) + +/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ +#define USB0_PORTSC1_H_PHCD_SHIFT (23) +#define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT) + +/* PFSC: Port force full speed connect */ +#define USB0_PORTSC1_H_PFSC_SHIFT (24) +#define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT) + +/* PSPD: Port speed */ +#define USB0_PORTSC1_H_PSPD_SHIFT (26) +#define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT) +#define USB0_PORTSC1_H_PSPD(x) ((x) << USB0_PORTSC1_H_PSPD_SHIFT) + +/* --- USB0_OTGSC values ---------------------------------------- */ + +/* VD: VBUS_Discharge */ +#define USB0_OTGSC_VD_SHIFT (0) +#define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT) + +/* VC: VBUS_Charge */ +#define USB0_OTGSC_VC_SHIFT (1) +#define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT) + +/* HAAR: Hardware assist auto_reset */ +#define USB0_OTGSC_HAAR_SHIFT (2) +#define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT) + +/* OT: OTG termination */ +#define USB0_OTGSC_OT_SHIFT (3) +#define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT) + +/* DP: Data pulsing */ +#define USB0_OTGSC_DP_SHIFT (4) +#define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT) + +/* IDPU: ID pull-up */ +#define USB0_OTGSC_IDPU_SHIFT (5) +#define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT) + +/* HADP: Hardware assist data pulse */ +#define USB0_OTGSC_HADP_SHIFT (6) +#define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT) + +/* HABA: Hardware assist B-disconnect to A-connect */ +#define USB0_OTGSC_HABA_SHIFT (7) +#define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT) + +/* ID: USB ID */ +#define USB0_OTGSC_ID_SHIFT (8) +#define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT) + +/* AVV: A-VBUS valid */ +#define USB0_OTGSC_AVV_SHIFT (9) +#define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT) + +/* ASV: A-session valid */ +#define USB0_OTGSC_ASV_SHIFT (10) +#define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT) + +/* BSV: B-session valid */ +#define USB0_OTGSC_BSV_SHIFT (11) +#define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT) + +/* BSE: B-session end */ +#define USB0_OTGSC_BSE_SHIFT (12) +#define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT) + +/* MS1T: 1 millisecond timer toggle */ +#define USB0_OTGSC_MS1T_SHIFT (13) +#define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT) + +/* DPS: Data bus pulsing status */ +#define USB0_OTGSC_DPS_SHIFT (14) +#define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT) + +/* IDIS: USB ID interrupt status */ +#define USB0_OTGSC_IDIS_SHIFT (16) +#define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT) + +/* AVVIS: A-VBUS valid interrupt status */ +#define USB0_OTGSC_AVVIS_SHIFT (17) +#define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT) + +/* ASVIS: A-Session valid interrupt status */ +#define USB0_OTGSC_ASVIS_SHIFT (18) +#define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT) + +/* BSVIS: B-Session valid interrupt status */ +#define USB0_OTGSC_BSVIS_SHIFT (19) +#define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT) + +/* BSEIS: B-Session end interrupt status */ +#define USB0_OTGSC_BSEIS_SHIFT (20) +#define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT) + +/* MS1S: 1 millisecond timer interrupt status */ +#define USB0_OTGSC_MS1S_SHIFT (21) +#define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT) + +/* DPIS: Data pulse interrupt status */ +#define USB0_OTGSC_DPIS_SHIFT (22) +#define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT) + +/* IDIE: USB ID interrupt enable */ +#define USB0_OTGSC_IDIE_SHIFT (24) +#define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT) + +/* AVVIE: A-VBUS valid interrupt enable */ +#define USB0_OTGSC_AVVIE_SHIFT (25) +#define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT) + +/* ASVIE: A-session valid interrupt enable */ +#define USB0_OTGSC_ASVIE_SHIFT (26) +#define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT) + +/* BSVIE: B-session valid interrupt enable */ +#define USB0_OTGSC_BSVIE_SHIFT (27) +#define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT) + +/* BSEIE: B-session end interrupt enable */ +#define USB0_OTGSC_BSEIE_SHIFT (28) +#define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT) + +/* MS1E: 1 millisecond timer interrupt enable */ +#define USB0_OTGSC_MS1E_SHIFT (29) +#define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT) + +/* DPIE: Data pulse interrupt enable */ +#define USB0_OTGSC_DPIE_SHIFT (30) +#define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT) + +/* --- USB0_USBMODE_D values ------------------------------------ */ + +/* CM1_0: Controller mode */ +#define USB0_USBMODE_D_CM1_0_SHIFT (0) +#define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT) +#define USB0_USBMODE_D_CM1_0(x) ((x) << USB0_USBMODE_D_CM1_0_SHIFT) + +/* ES: Endian select */ +#define USB0_USBMODE_D_ES_SHIFT (2) +#define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT) + +/* SLOM: Setup Lockout mode */ +#define USB0_USBMODE_D_SLOM_SHIFT (3) +#define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT) + +/* SDIS: Setup Lockout mode */ +#define USB0_USBMODE_D_SDIS_SHIFT (4) +#define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT) + +/* --- USB0_USBMODE_H values ------------------------------------ */ + +/* CM: Controller mode */ +#define USB0_USBMODE_H_CM_SHIFT (0) +#define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT) +#define USB0_USBMODE_H_CM(x) ((x) << USB0_USBMODE_H_CM_SHIFT) + +/* ES: Endian select */ +#define USB0_USBMODE_H_ES_SHIFT (2) +#define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT) + +/* SDIS: Stream disable mode */ +#define USB0_USBMODE_H_SDIS_SHIFT (4) +#define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT) + +/* VBPS: VBUS power select */ +#define USB0_USBMODE_H_VBPS_SHIFT (5) +#define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT) + +/* --- USB0_ENDPTSETUPSTAT values ------------------------------- */ + +/* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */ +#define USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_SHIFT (0) +#define USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_MASK (0x3f << USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_SHIFT) +#define USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT(x) ((x) << USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_SHIFT) + +/* --- USB0_ENDPTPRIME values ----------------------------------- */ + +/* PERB: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTPRIME_PERB_SHIFT (0) +#define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT) +#define USB0_ENDPTPRIME_PERB(x) ((x) << USB0_ENDPTPRIME_PERB_SHIFT) + +/* PETB: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTPRIME_PETB_SHIFT (16) +#define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT) +#define USB0_ENDPTPRIME_PETB(x) ((x) << USB0_ENDPTPRIME_PETB_SHIFT) + +/* --- USB0_ENDPTFLUSH values ----------------------------------- */ + +/* FERB: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTFLUSH_FERB_SHIFT (0) +#define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT) +#define USB0_ENDPTFLUSH_FERB(x) ((x) << USB0_ENDPTFLUSH_FERB_SHIFT) + +/* FETB: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTFLUSH_FETB_SHIFT (16) +#define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT) +#define USB0_ENDPTFLUSH_FETB(x) ((x) << USB0_ENDPTFLUSH_FETB_SHIFT) + +/* --- USB0_ENDPTSTAT values ------------------------------------ */ + +/* ERBR: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTSTAT_ERBR_SHIFT (0) +#define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT) +#define USB0_ENDPTSTAT_ERBR(x) ((x) << USB0_ENDPTSTAT_ERBR_SHIFT) + +/* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */ +#define USB0_ENDPTSTAT_ETBR_SHIFT (16) +#define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT) +#define USB0_ENDPTSTAT_ETBR(x) ((x) << USB0_ENDPTSTAT_ETBR_SHIFT) + +/* --- USB0_ENDPTCOMPLETE values -------------------------------- */ + +/* ERCE: Endpoint receive complete event for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTCOMPLETE_ERCE_SHIFT (0) +#define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT) +#define USB0_ENDPTCOMPLETE_ERCE(x) ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT) + +/* ETCE: Endpoint transmit complete event for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTCOMPLETE_ETCE_SHIFT (16) +#define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT) +#define USB0_ENDPTCOMPLETE_ETCE(x) ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT) + +/* --- USB0_ENDPTCTRL0 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL0_RXS_SHIFT (0) +#define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT) + +/* RXT1_0: Endpoint type */ +#define USB0_ENDPTCTRL0_RXT1_0_SHIFT (2) +#define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT) +#define USB0_ENDPTCTRL0_RXT1_0(x) ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL0_RXE_SHIFT (7) +#define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL0_TXS_SHIFT (16) +#define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT) + +/* TXT1_0: Endpoint type */ +#define USB0_ENDPTCTRL0_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL0_TXT1_0(x) ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL0_TXE_SHIFT (23) +#define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL1 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL1_RXS_SHIFT (0) +#define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL1_RXT_SHIFT (2) +#define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT) +#define USB0_ENDPTCTRL1_RXT(x) ((x) << USB0_ENDPTCTRL1_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL1_RXI_SHIFT (5) +#define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL1_RXR_SHIFT (6) +#define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL1_RXE_SHIFT (7) +#define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL1_TXS_SHIFT (16) +#define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL1_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL1_TXT1_0(x) ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL1_TXI_SHIFT (21) +#define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL1_TXR_SHIFT (22) +#define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL1_TXE_SHIFT (23) +#define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL2 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL2_RXS_SHIFT (0) +#define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL2_RXT_SHIFT (2) +#define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT) +#define USB0_ENDPTCTRL2_RXT(x) ((x) << USB0_ENDPTCTRL2_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL2_RXI_SHIFT (5) +#define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL2_RXR_SHIFT (6) +#define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL2_RXE_SHIFT (7) +#define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL2_TXS_SHIFT (16) +#define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL2_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL2_TXT1_0(x) ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL2_TXI_SHIFT (21) +#define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL2_TXR_SHIFT (22) +#define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL2_TXE_SHIFT (23) +#define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL3 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL3_RXS_SHIFT (0) +#define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL3_RXT_SHIFT (2) +#define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT) +#define USB0_ENDPTCTRL3_RXT(x) ((x) << USB0_ENDPTCTRL3_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL3_RXI_SHIFT (5) +#define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL3_RXR_SHIFT (6) +#define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL3_RXE_SHIFT (7) +#define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL3_TXS_SHIFT (16) +#define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL3_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL3_TXT1_0(x) ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL3_TXI_SHIFT (21) +#define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL3_TXR_SHIFT (22) +#define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL3_TXE_SHIFT (23) +#define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL4 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL4_RXS_SHIFT (0) +#define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL4_RXT_SHIFT (2) +#define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT) +#define USB0_ENDPTCTRL4_RXT(x) ((x) << USB0_ENDPTCTRL4_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL4_RXI_SHIFT (5) +#define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL4_RXR_SHIFT (6) +#define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL4_RXE_SHIFT (7) +#define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL4_TXS_SHIFT (16) +#define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL4_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL4_TXT1_0(x) ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL4_TXI_SHIFT (21) +#define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL4_TXR_SHIFT (22) +#define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL4_TXE_SHIFT (23) +#define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL5 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL5_RXS_SHIFT (0) +#define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL5_RXT_SHIFT (2) +#define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT) +#define USB0_ENDPTCTRL5_RXT(x) ((x) << USB0_ENDPTCTRL5_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL5_RXI_SHIFT (5) +#define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL5_RXR_SHIFT (6) +#define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL5_RXE_SHIFT (7) +#define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL5_TXS_SHIFT (16) +#define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL5_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL5_TXT1_0(x) ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL5_TXI_SHIFT (21) +#define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL5_TXR_SHIFT (22) +#define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL5_TXE_SHIFT (23) +#define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT) /* --- USB1 registers ------------------------------------------------------ */ /* TODO */ diff --git a/lib/lpc43xx/i2c.c b/lib/lpc43xx/i2c.c index 8f98a006..9fa36489 100644 --- a/lib/lpc43xx/i2c.c +++ b/lib/lpc43xx/i2c.c @@ -47,7 +47,7 @@ void i2c0_init(void) SCU_SFSI2C0 = SCU_I2C0_NOMINAL; /* use IRC as clock source for APB1 (including I2C0) */ - CGU_BASE_APB1_CLK = (CGU_SRC_IRC << CGU_BASE_CLK_SEL_SHIFT); + CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC); /* FIXME assuming we're on IRC at 12 MHz */ diff --git a/scripts/data/lpc43xx/gen.py b/scripts/data/lpc43xx/gen.py new file mode 100644 index 00000000..86c07e47 --- /dev/null +++ b/scripts/data/lpc43xx/gen.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python + +import sys +import csv +from collections import OrderedDict + +from pprint import pprint + +reader = csv.reader(open(sys.argv[1], 'r')) + +registers = OrderedDict() +for register_name, lsb, width, field_name, description, reset_value, access in reader: + if register_name not in registers: + registers[register_name] = { + 'fields': OrderedDict(), + } + + register = registers[register_name] + fields = register['fields'] + if field_name in fields: + raise RuntimeError('Duplicate field name "%s" in register "%s"' % + field_name, register_name) + else: + fields[field_name] = { + 'lsb': int(lsb), + 'width': int(width), + 'description': description, + 'reset_value': reset_value, + 'access': access, + } + +for register_name, register in registers.iteritems(): + print('/* --- %s values %s */' % (register_name, '-' * (50 - len(register_name)))) + print + fields = register['fields'] + #for field_name, field in sorted(fields.items(), lambda x, y: cmp(x[1]['lsb'], y[1]['lsb'])): + for field_name, field in fields.items(): + mask_bits = (1 << field['width']) - 1 + print('/* %s: %s */' % (field_name, field['description'])) + print('#define %s_%s_SHIFT (%d)' % ( + register_name, field_name, field['lsb'], + )) + if mask_bits > 1: + print('#define %s_%s_MASK (0x%x << %s_%s_SHIFT)' % ( + register_name, field_name, mask_bits, register_name, field_name, + )) + print('#define %s_%s(x) ((x) << %s_%s_SHIFT)' % ( + register_name, field_name, register_name, field_name, + )) + else: + print('#define %s_%s (1 << %s_%s_SHIFT)' % ( + register_name, field_name, register_name, field_name, + )) + print