Add preliminary support for Cryptographic coprocessor on stm32 F2 and F4
This commit is contained in:
BuFran
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
3bc5a249a1
commit
035c67ced6
291
include/libopencm3/stm32/common/crypto_common_f24.h
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291
include/libopencm3/stm32/common/crypto_common_f24.h
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@@ -0,0 +1,291 @@
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/** @addtogroup crypto_defines
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*
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* @warning The CRYP subsystem is present only in a limited set of devices,
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* see next section for list of supported devices.
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*
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* @section crypto_api_supported Supported devices
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*
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* - STM32F205
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* - STM32F207
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* - STM32F215
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* - STM32F217
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* - STM32F405
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* - STM32F407
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* - STM32F415
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* - STM32F417 <i>(tested)</i>
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* - STM32F427
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* - STM32F437
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*
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* @section crypto_api_theory Theory of operation
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*
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*
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*
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* @section crypto_api_basic Basic handling API
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*
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*
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* @b Example @b 1: Blocking mode
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*
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* @code
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* //[enable-clocks]
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* crypto_set_key(CRYPTO_KEY_128BIT,key);
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* crypto_set_iv(iv); // only in CBC or CTR mode
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* crypto_set_datatype(CRYPTO_DATA_16BIT);
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* crypto_set_algorithm(ENCRYPT_AES_ECB);
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* crypto_start();
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* foreach(block in blocks)
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* crypto_process_block(plaintext,ciphertext,blocksize);
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* crypto_stop();
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* @endcode
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*
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* @section crypto_api_interrupt Interrupt supported handling API
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*
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* @warning This operation mode is currently not supported.
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*
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* @b Example @b 2: Interrupt mode
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*
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* @code
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* //[enable-clocks]
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* crypto_set_key(CRYPTO_KEY_128BIT,key);
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* crypto_set_iv(iv); // only in CBC or CTR mode
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* crypto_set_datatype(CRYPTO_DATA_16BIT);
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* crypto_set_algorithm(ENCRYPT_AES_ECB);
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* crypto_start();
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* [... API to be described later ...]
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* crypto_stop();
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* @endcode
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*
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* @section crypto_api_dma DMA handling API
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*
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* @warning This operation mode is currently not supported.
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*
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* @b Example @b 3: DMA mode
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*
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* @code
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* //[enable-clocks]
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* crypto_set_key(CRYPTO_KEY_128BIT,key);
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* crypto_set_iv(iv); // only in CBC or CTR mode
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* crypto_set_datatype(CRYPTO_DATA_16BIT);
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* crypto_set_algorithm(ENCRYPT_AES_ECB);
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* crypto_start();
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* [... API to be described later ...]
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* crypto_stop();
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* @endcode
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRYP.H
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The order of header inclusion is important. cryp.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_CRYPTO_H
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/** @endcond */
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#ifndef LIBOPENCM3_CRYPTO_COMMON_F24_H
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#define LIBOPENCM3_CRYPTO_COMMON_F24_H
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/* --- CRYP registers ------------------------------------------------------ */
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/** @defgroup crypto_registers_gen Registers (Generic)
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*
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* @brief Register access to the CRYP controller. (All chips)
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*
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* @ingroup crypto_defines
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*/
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/**@{*/
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#define CRYP CRYP_BASE
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/* CRYP Control Register (CRYP_CR) */
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#define CRYP_CR MMIO32(CRYP_BASE + 0x00)
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/* CRYP Status Register (CRYP_SR) */
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#define CRYP_SR MMIO32(CRYP_BASE + 0x04)
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/* CRYP Data Input Register (CRYP_DIN) */
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#define CRYP_DIN MMIO32(CRYP_BASE + 0x08)
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/** CRYP Data Output Register (CRYP_DOUT) @see blablabla */
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#define CRYP_DOUT MMIO32(CRYP_BASE + 0x0C)
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/* CRYP DMA Control Register (CRYP_DMACR) */
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#define CRYP_DMACR MMIO32(CRYP_BASE + 0x10)
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/* CRYP Interrupt mask set/clear register (CRYP_IMSCR) */
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#define CRYP_IMSCR MMIO32(CRYP_BASE + 0x14)
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/* CRYP Raw Interrupt status register (CRYP_RISR) */
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#define CRYP_RISR MMIO32(CRYP_BASE + 0x18)
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/* CRYP Masked Interrupt status register (CRYP_MISR) */
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#define CRYP_MISR MMIO32(CRYP_BASE + 0x1C)
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/* CRYP Key registers (CRYP_KxLR) x=0..3 */
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#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8)
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/* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */
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#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8)
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/* --- CRYP_CR values ------------------------------------------------------ */
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/* ALGODIR: Algorithm direction */
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#define CRYP_CR_ALGODIR (1 << 2)
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/* ALGOMODE: Algorithm mode */
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#define CRYP_CR_ALGOMODE_SHIFT 3
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#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_DES_CBC (3 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_AES_ECB (4 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_AES_CBC (5 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_AES_CTR (6 << CRYP_CR_ALGOMODE_SHIFT)
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#define CRYP_CR_ALGOMODE_AES_PREP (7 << CRYP_CR_ALGOMODE_SHIFT)
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/* DATATYPE: Data type selection */
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#define CRYP_CR_DATATYPE_SHIFT 6
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#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT)
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#define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT)
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#define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT)
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#define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT)
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#define CRYP_CR_DATATYPE_BIT (3 << CRYP_CR_DATATYPE_SHIFT)
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/* KEYSIZE: Key size selection (AES mode only)*/
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#define CRYP_CR_KEYSIZE_SHIFT 8
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#define CRYP_CR_KEYSIZE (3 << CRYP_CR_KEYSIZE_SHIFT)
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#define CRYP_CR_KEYSIZE_128 (0 << CRYP_CR_KEYSIZE_SHIFT)
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#define CRYP_CR_KEYSIZE_192 (1 << CRYP_CR_KEYSIZE_SHIFT)
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#define CRYP_CR_KEYSIZE_256 (2 << CRYP_CR_KEYSIZE_SHIFT)
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/* FFLUSH: FIFO Flush */
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#define CRYP_CR_FFLUSH (1 << 14)
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/* CRYPEN: Cryptographic processor enable*/
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#define CRYP_CR_CRYPEN (1 << 15)
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/* --- CRYP_SR values ------------------------------------------------------ */
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/* IFEM: Input FIFO empty */
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#define CRYP_SR_IFEM (1 << 0)
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/* IFNF: Input FIFO not full */
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#define CRYP_SR_IFNF (1 << 1)
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/* OFNE: Output FIFO not empty */
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#define CRYP_SR_OFNE (1 << 2)
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/* OFFU: Output FIFO full */
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#define CRYP_SR_OFFU (1 << 3)
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/* BUSY: Busy bit */
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#define CRYP_SR_BUSY (1 << 4)
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/* --- CRYP_DMACR values --------------------------------------------------- */
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/* DIEN: DMA input enable */
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#define CRYP_DMACR_DIEN (1 << 0)
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/* DOEN: DMA output enable */
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#define CRYP_DMACR_DOEN (1 << 1)
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/* --- CRYP_IMSCR values --------------------------------------------------- */
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/* INIM: Input FIFO service interrupt mask */
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#define CRYP_IMSCR_INIM (1 << 0)
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/* OUTIM: Output FIFO service interrupt mask */
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#define CRYP_IMSCR_OUTIM (1 << 1)
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/* --- CRYP_RISR values ---------------------------------------------------- */
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/* INRIS: Input FIFO service raw interrupt status */
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#define CRYP_RISR_INRIS (1 << 0)
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/* OUTRIS: Output FIFO service raw data */
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#define CRYP_RISR_OUTRIS (1 << 0)
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/* --- CRYP_MISR values ---------------------------------------------------- */
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/* INMIS: Input FIFO service masked interrupt status */
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#define CRYP_MISR_INMIS (1 << 0)
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/* OUTMIS: Output FIFO service masked interrupt status */
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#define CRYP_MISR_OUTMIS (1 << 0)
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/**@}*/
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/** @defgroup crypto_api_gen API (Generic)
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*
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* @brief API for the CRYP controller
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*
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* @ingroup crypto_defines
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*/
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/**@{*/
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typedef enum {
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ENCRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB,
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ENCRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC,
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ENCRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB,
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ENCRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC,
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ENCRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB,
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ENCRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC,
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ENCRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,
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DECRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGODIR,
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DECRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGODIR,
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DECRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB | CRYP_CR_ALGODIR,
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DECRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC | CRYP_CR_ALGODIR,
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DECRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR,
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DECRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR,
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DECRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR, /* XOR is same ENC as DEC */
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} crypto_mode_t;
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typedef enum {
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CRYPTO_KEY_128BIT = 0,
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CRYPTO_KEY_192BIT,
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CRYPTO_KEY_256BIT,
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} crypto_keysize_t;
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typedef enum {
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CRYPTO_DATA_32BIT = 0,
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CRYPTO_DATA_16BIT,
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CRYPTO_DATA_8BIT,
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CRYPTO_DATA_BIT,
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} crypto_datatype_t;
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BEGIN_DECLS
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void crypto_wait_busy(void);
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void crypto_set_key(crypto_keysize_t keysize, uint64_t key[]);
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void crypto_set_iv(uint64_t iv[]);
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void crypto_set_datatype(crypto_datatype_t datatype);
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void crypto_set_algorithm(crypto_mode_t mode);
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void crypto_start(void);
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void crypto_stop(void);
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uint32_t crypto_process_block(uint32_t * inp, uint32_t * outp, uint32_t length);
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END_DECLS
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/**@}*/
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/**@}*/
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#endif
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/** @cond */
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#else
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#warning "crypto_common_f24.h should not be included explicitly, only via crypto.h"
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#endif
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/** @endcond */
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27
include/libopencm3/stm32/crypto.h
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27
include/libopencm3/stm32/crypto.h
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@@ -0,0 +1,27 @@
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/* This provides unification of code over STM32F subfamilies */
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
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*
|
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* This library is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(STM32F2)
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# include <libopencm3/stm32/f2/crypto.h>
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#elif defined(STM32F4)
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# include <libopencm3/stm32/f4/crypto.h>
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#else
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# error "CRYPTO processor is supported only" \
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"in stm32f2xx, stm32f41xx, stm32f42xx and stm32f43xx family."
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#endif
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38
include/libopencm3/stm32/f2/crypto.h
Normal file
38
include/libopencm3/stm32/f2/crypto.h
Normal file
@@ -0,0 +1,38 @@
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/** @defgroup crypto_defines CRYPTO Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F2xx CRYP Controller</b>
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*
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* @ingroup STM32F2xx_defines
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*
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* @version 1.0.0
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*
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* @date 17 Jun 2013
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*
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* LGPL License Terms @ref lgpl_license
|
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*/
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/*
|
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* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
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#ifndef LIBOPENCM3_CRYPTO_H
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#define LIBOPENCM3_CRYPTO_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/common/crypto_common_f24.h>
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#endif
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@@ -118,7 +118,9 @@
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#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000)
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/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
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#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
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/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5006 07FF): Reserved */
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/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */
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#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)
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#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
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#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
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/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
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||||
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||||
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98
include/libopencm3/stm32/f4/crypto.h
Normal file
98
include/libopencm3/stm32/f4/crypto.h
Normal file
@@ -0,0 +1,98 @@
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/** @defgroup crypto_defines CRYPTO Defines
|
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*
|
||||
* @brief <b>Defined constants and Types for the STM32F4xx Crypto Coprocessor
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*
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* @ingroup STM32F4xx_defines
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*
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* @version 1.0.0
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*
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* @date 22 Jun 2013
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||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_CRYPTO_H
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#define LIBOPENCM3_CRYPTO_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/crypto_common_f24.h>
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/**@{*/
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/* --- CRYP registers ------------------------------------------------------ */
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||||
/** @defgroup crypto_defines_registers Registers (for F42xx or F43xx only)
|
||||
*
|
||||
* @brief Register access to the CRYP controller. Registers for F42xx and 43xx
|
||||
*
|
||||
* @ingroup crypto_defines
|
||||
*/
|
||||
/**@{*/
|
||||
|
||||
/* CRYP_CSGCMCCMxR: Crypto context registers CCM mode, i=0-7*/
|
||||
#define CRYP_CSGCMCCMR(i) MMIO32(CRYP_BASE + 0x50 + (i) * 4)
|
||||
|
||||
/* CRYP_CSGCMxR: Crypto context registers all modes, i=0-7*/
|
||||
#define CRYP_CSGCMR(i) MMIO32(CRYP_BASE + 0x70 + (i) * 4)
|
||||
|
||||
/* --- CRYP_CR values ------------------------------------------------------ */
|
||||
|
||||
/* Only for part STM32F42xx and STM32F43xx: */
|
||||
|
||||
/* GCM_CMPH: GCM or CCM phase state */
|
||||
#define CRYP_CR_GCM_CMPH_SHIFT 16
|
||||
#define CRYP_CR_GCM_CMPH (3 << CRYP_CR_GCM_CMPH_SHIFT)
|
||||
#define CRYP_CR_GCM_CMPH_INIT (0 << CRYP_CR_GCM_CMPH_SHIFT)
|
||||
#define CRYP_CR_GCM_CMPH_HEADER (1 << CRYP_CR_GCM_CMPH_SHIFT)
|
||||
#define CRYP_CR_GCM_CMPH_PAYLOAD (2 << CRYP_CR_GCM_CMPH_SHIFT)
|
||||
#define CRYP_CR_GCM_CMPH_FINAL (3 << CRYP_CR_GCM_CMPH_SHIFT)
|
||||
|
||||
/* ALGOMODE3: Algorithm mode, fourth bit */
|
||||
#define CRYP_CR_ALGOMODE3 (1 << 19)
|
||||
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup crypto_api API (for F42xx or F43xx only)
|
||||
*
|
||||
* @brief API for the CRYP controller.
|
||||
*
|
||||
* @warning Only for F42xx and 43xx
|
||||
*
|
||||
* @ingroup crypto_defines
|
||||
*/
|
||||
/**@{*/
|
||||
|
||||
typedef enum {
|
||||
ENCRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3,
|
||||
ENCRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3,
|
||||
DECRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3 |
|
||||
CRYP_CR_ALGODIR,
|
||||
DECRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3 |
|
||||
CRYP_CR_ALGODIR,
|
||||
} crypto_mode_mac_t;
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void crypto_context_swap(uint32_t * buf);
|
||||
void crypto_set_mac_algorithm(crypto_mode_mac_t mode);
|
||||
|
||||
END_DECLS
|
||||
/**@}*/
|
||||
/**@}*/
|
||||
#endif
|
||||
@@ -116,11 +116,14 @@
|
||||
/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */
|
||||
|
||||
/* AHB2 */
|
||||
#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000)
|
||||
#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)
|
||||
/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
|
||||
#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
|
||||
/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5006 07FF): Reserved */
|
||||
#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
|
||||
#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
|
||||
/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */
|
||||
#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)
|
||||
#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
|
||||
/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */
|
||||
#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
|
||||
/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
|
||||
|
||||
/* AHB3 */
|
||||
|
||||
Reference in New Issue
Block a user