4 Commits

Author	SHA1	Message	Date
Piotr Esden-Tempski	2583cc54cc	[rcc_periph_clock_enable] Using the new rcc enable format. ... We are missing handling of stm32l1 AHBLP clock rail.	2015-01-20 15:33:00 -08:00
Frantisek Burian	7f215cb6fa	Use libopencm3 coding style	2014-07-14 13:44:44 +02:00
Frantisek Burian	bc5d0816e5	MSC: Use another PID to load correct drivers	2014-07-14 13:44:43 +02:00
Pavol Rusnak	7c07ed97a6	example for MSC (Mass Storage Class) support	2014-07-14 13:44:43 +02:00