stm32: timer: further clarify example commentary
The "timer" example is actually "the same" for both f1 and f4. Do a sanity sweep over the commentary, remove all vestiges that this was cloned from a motor control example, and synchronize both examples. Future work should extract the common portions "somewhere" but at least make them consistent for now.
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@@ -18,14 +18,18 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/exti.h>
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#include <libopencmsis/core_cm3.h>
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#ifndef ARRAY_LEN
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#define ARRAY_LEN(array) (sizeof((array))/sizeof((array)[0]))
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#endif
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uint16_t frequency_sequence[18] = {
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1000,
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500,
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@@ -80,75 +84,41 @@ static void tim_setup(void)
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/* Enable TIM2 interrupt. */
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nvic_enable_irq(NVIC_TIM2_IRQ);
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/* Reset TIM2 peripheral. */
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/* Reset TIM2 peripheral to defaults. */
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rcc_periph_reset_pulse(RST_TIM2);
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/* Timer global mode:
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* - No divider
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* - Alignment edge
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* - Direction up
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* (These are actually default values after reset above, so this call
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* is strictly unnecessary, but demos the api for alternative settings)
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*/
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timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
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TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
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/* Reset prescaler value.
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* Running the clock at 10kHz.
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*/
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/*
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* On STM32F4 the timers are not running directly from pure APB1 or
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* APB2 clock busses. The APB1 and APB2 clocks used for timers might
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* be the double of the APB1 and APB2 clocks. This depends on the
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* setting in DCKCFGR register. By default the behaviour is the
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* following: If the Prescaler APBx is greater than 1 the derived timer
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* APBx clocks will be double of the original APBx frequencies. Only if
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* the APBx prescaler is set to 1 the derived timer APBx will equal the
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* original APBx frequencies.
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*
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* In our case here the APB1 is system frequency divided by 4 and APB2
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* is system frequency divided by 2. This means APB1 timer will be 2 x
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* APB1 and APB2 will be 2 x APB2. So when we try to calculate the
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* prescaler value we have to use rcc_apb1_freqency * 2!!!
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*
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* For additional information see reference manual for the stm32f4
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* familiy of chips. Page 204 and 213
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*/
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/*
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* Please take note that the clock source for STM32F4 timers
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* might not be the raw APB1/APB2 clocks. In various conditions they
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* are doubled. See the Reference Manual for full details!
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* In our case, TIM2 on APB1 is running at double frequency, so this
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* sets the prescaler to have the timer run at 10kHz
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*/
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timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000));
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/* Disable preload. */
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timer_disable_preload(TIM2);
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/* Continous mode. */
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timer_continuous_mode(TIM2);
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/* Period (36kHz). */
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/* count full range, as we'll update compare value continuously */
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timer_set_period(TIM2, 65535);
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/* Disable outputs. */
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timer_disable_oc_output(TIM2, TIM_OC1);
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timer_disable_oc_output(TIM2, TIM_OC2);
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timer_disable_oc_output(TIM2, TIM_OC3);
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timer_disable_oc_output(TIM2, TIM_OC4);
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/* -- OC1 configuration -- */
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/* Configure global mode of line 1. */
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timer_disable_oc_clear(TIM2, TIM_OC1);
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timer_disable_oc_preload(TIM2, TIM_OC1);
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timer_set_oc_slow_mode(TIM2, TIM_OC1);
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timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
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/* Set the capture compare value for OC1. */
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/* Set the initual output compare value for OC1. */
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timer_set_oc_value(TIM2, TIM_OC1, 1000);
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/* ---- */
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/* ARR reload enable. */
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timer_disable_preload(TIM2);
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/* Counter enable. */
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timer_enable_counter(TIM2);
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/* Enable commutation interrupt. */
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/* Enable Channel 1 compare interrupt to recalculate compare values */
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timer_enable_irq(TIM2, TIM_DIER_CC1IE);
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}
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@@ -170,8 +140,9 @@ void tim2_isr(void)
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new_time = compare_time + frequency;
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timer_set_oc_value(TIM2, TIM_OC1, new_time);
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if (frequency_sel == 18)
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if (frequency_sel == ARRAY_LEN(frequency_sequence)) {
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frequency_sel = 0;
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}
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/* Toggle LED to indicate compare event. */
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gpio_toggle(GPIOD, GPIO12);
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