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Updated to the new DAC api.

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This commit is contained in:
Piotr Esden-Tempski
2021-06-18 23:59:35 -07:00
parent 0bbafd690a
commit 520e7523ec
5 changed files with 28 additions and 28 deletions
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12
examples/stm32/f1/stm32vl-discovery/adc-dac-printf/adc-dac-printf.c
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@@ -118,10 +118,10 @@ static void adc_setup(void)
static void dac_setup(void) static void dac_setup(void)
{ {
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5);
dac_disable(CHANNEL_2); dac_disable(DAC1, DAC_CHANNEL2);
dac_disable_waveform_generation(CHANNEL_2); dac_disable_waveform_generation(DAC1, DAC_CHANNEL2);
dac_enable(CHANNEL_2); dac_enable(DAC1, DAC_CHANNEL2);
dac_set_trigger_source(DAC_CR_TSEL2_SW); dac_set_trigger_source(DAC1, DAC_CR_TSEL2_SW);
} }
static uint16_t read_adc_naiive(uint8_t channel) static uint16_t read_adc_naiive(uint8_t channel)
@@ -150,8 +150,8 @@ int main(void)
while (1) { while (1) {
uint16_t input_adc0 = read_adc_naiive(0); uint16_t input_adc0 = read_adc_naiive(0);
uint16_t target = input_adc0 / 2; uint16_t target = input_adc0 / 2;
dac_load_data_buffer_single(target, RIGHT12, CHANNEL_2); dac_load_data_buffer_single(DAC1, target, DAC_ALIGN_RIGHT12, DAC_CHANNEL2);
dac_software_trigger(CHANNEL_2); dac_software_trigger(DAC1, DAC_CHANNEL2);
uint16_t input_adc1 = read_adc_naiive(1); uint16_t input_adc1 = read_adc_naiive(1);
printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n", printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n",
j++, input_adc0, target, input_adc1); j++, input_adc0, target, input_adc1);

12
examples/stm32/f4/stm32f4-discovery/adc-dac-printf/adc-dac-printf.c
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@@ -109,10 +109,10 @@ static void adc_setup(void)
static void dac_setup(void) static void dac_setup(void)
{ {
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5); gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5);
dac_disable(CHANNEL_2); dac_disable(DAC1, DAC_CHANNEL2);
dac_disable_waveform_generation(CHANNEL_2); dac_disable_waveform_generation(DAC1, DAC_CHANNEL2);
dac_enable(CHANNEL_2); dac_enable(DAC1, DAC_CHANNEL2);
dac_set_trigger_source(DAC_CR_TSEL2_SW); dac_set_trigger_source(DAC1, DAC_CR_TSEL2_SW);
} }
static uint16_t read_adc_naiive(uint8_t channel) static uint16_t read_adc_naiive(uint8_t channel)
@@ -143,8 +143,8 @@ int main(void)
while (1) { while (1) {
uint16_t input_adc0 = read_adc_naiive(0); uint16_t input_adc0 = read_adc_naiive(0);
uint16_t target = input_adc0 / 2; uint16_t target = input_adc0 / 2;
dac_load_data_buffer_single(target, RIGHT12, CHANNEL_2); dac_load_data_buffer_single(DAC1, target, DAC_ALIGN_RIGHT12, DAC_CHANNEL2);
dac_software_trigger(CHANNEL_2); dac_software_trigger(DAC1, DAC_CHANNEL2);
uint16_t input_adc1 = read_adc_naiive(1); uint16_t input_adc1 = read_adc_naiive(1);
printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n", printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n",
j++, input_adc0, target, input_adc1); j++, input_adc0, target, input_adc1);

10
examples/stm32/f4/stm32f4-discovery/dac-dma/dac-dma.c
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@@ -91,7 +91,7 @@ static void dma_setup(void)
DMA_SxCR_DIR_MEM_TO_PERIPHERAL); DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
/* The register to target is the DAC1 8-bit right justified data /* The register to target is the DAC1 8-bit right justified data
register */ register */
dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1); dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1(DAC1));
/* The array v[] is filled with the waveform data to be output */ /* The array v[] is filled with the waveform data to be output */
dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform); dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform);
dma_set_number_of_data(DMA1, DMA_STREAM5, 256); dma_set_number_of_data(DMA1, DMA_STREAM5, 256);
@@ -107,10 +107,10 @@ static void dac_setup(void)
rcc_periph_clock_enable(RCC_DAC); rcc_periph_clock_enable(RCC_DAC);
/* Setup the DAC channel 1, with timer 2 as trigger source. /* Setup the DAC channel 1, with timer 2 as trigger source.
* Assume the DAC has woken up by the time the first transfer occurs */ * Assume the DAC has woken up by the time the first transfer occurs */
dac_trigger_enable(CHANNEL_1); dac_trigger_enable(DAC1, DAC_CHANNEL1);
dac_set_trigger_source(DAC_CR_TSEL1_T2); dac_set_trigger_source(DAC1, DAC_CR_TSEL1_T2);
dac_dma_enable(CHANNEL_1); dac_dma_enable(DAC1, DAC_CHANNEL1);
dac_enable(CHANNEL_1); dac_enable(DAC1, DAC_CHANNEL1);
} }
/*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/

12
examples/stm32/f4/stm32f429i-discovery/adc-dac-printf/adc-dac-printf.c
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@@ -110,10 +110,10 @@ static void adc_setup(void)
static void dac_setup(void) static void dac_setup(void)
{ {
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5); gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5);
dac_disable(CHANNEL_2); dac_disable(DAC1, DAC_CHANNEL2);
dac_disable_waveform_generation(CHANNEL_2); dac_disable_waveform_generation(DAC1, DAC_CHANNEL2);
dac_enable(CHANNEL_2); dac_enable(DAC1, DAC_CHANNEL2);
dac_set_trigger_source(DAC_CR_TSEL2_SW); dac_set_trigger_source(DAC1, DAC_CR_TSEL2_SW);
} }
static uint16_t read_adc_naiive(uint8_t channel) static uint16_t read_adc_naiive(uint8_t channel)
@@ -144,8 +144,8 @@ int main(void)
while (1) { while (1) {
uint16_t input_adc0 = read_adc_naiive(0); uint16_t input_adc0 = read_adc_naiive(0);
uint16_t target = input_adc0 / 2; uint16_t target = input_adc0 / 2;
dac_load_data_buffer_single(target, RIGHT12, CHANNEL_2); dac_load_data_buffer_single(DAC1, target, DAC_ALIGN_RIGHT12, DAC_CHANNEL2);
dac_software_trigger(CHANNEL_2); dac_software_trigger(DAC1, DAC_CHANNEL2);
uint16_t input_adc1 = read_adc_naiive(1); uint16_t input_adc1 = read_adc_naiive(1);
printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n", printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n",
j++, input_adc0, target, input_adc1); j++, input_adc0, target, input_adc1);

10
examples/stm32/f4/stm32f429i-discovery/dac-dma/dac-dma.c
View File

@@ -92,7 +92,7 @@ static void dma_setup(void)
DMA_SxCR_DIR_MEM_TO_PERIPHERAL); DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
/* The register to target is the DAC1 8-bit right justified data /* The register to target is the DAC1 8-bit right justified data
register */ register */
dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1); dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1(DAC1));
/* The array v[] is filled with the waveform data to be output */ /* The array v[] is filled with the waveform data to be output */
dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform); dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform);
dma_set_number_of_data(DMA1, DMA_STREAM5, 256); dma_set_number_of_data(DMA1, DMA_STREAM5, 256);
@@ -108,10 +108,10 @@ static void dac_setup(void)
rcc_periph_clock_enable(RCC_DAC); rcc_periph_clock_enable(RCC_DAC);
/* Setup the DAC channel 1, with timer 2 as trigger source. /* Setup the DAC channel 1, with timer 2 as trigger source.
* Assume the DAC has woken up by the time the first transfer occurs */ * Assume the DAC has woken up by the time the first transfer occurs */
dac_trigger_enable(CHANNEL_1); dac_trigger_enable(DAC1, DAC_CHANNEL1);
dac_set_trigger_source(DAC_CR_TSEL1_T2); dac_set_trigger_source(DAC1, DAC_CR_TSEL1_T2);
dac_dma_enable(CHANNEL_1); dac_dma_enable(DAC1, DAC_CHANNEL1);
dac_enable(CHANNEL_1); dac_enable(DAC1, DAC_CHANNEL1);
} }
/*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/