Updated to the new DAC api.
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@@ -118,10 +118,10 @@ static void adc_setup(void)
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static void dac_setup(void)
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{
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gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5);
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dac_disable(CHANNEL_2);
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dac_disable_waveform_generation(CHANNEL_2);
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dac_enable(CHANNEL_2);
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dac_set_trigger_source(DAC_CR_TSEL2_SW);
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dac_disable(DAC1, DAC_CHANNEL2);
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dac_disable_waveform_generation(DAC1, DAC_CHANNEL2);
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dac_enable(DAC1, DAC_CHANNEL2);
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dac_set_trigger_source(DAC1, DAC_CR_TSEL2_SW);
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}
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static uint16_t read_adc_naiive(uint8_t channel)
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@@ -150,8 +150,8 @@ int main(void)
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while (1) {
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uint16_t input_adc0 = read_adc_naiive(0);
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uint16_t target = input_adc0 / 2;
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dac_load_data_buffer_single(target, RIGHT12, CHANNEL_2);
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dac_software_trigger(CHANNEL_2);
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dac_load_data_buffer_single(DAC1, target, DAC_ALIGN_RIGHT12, DAC_CHANNEL2);
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dac_software_trigger(DAC1, DAC_CHANNEL2);
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uint16_t input_adc1 = read_adc_naiive(1);
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printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n",
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j++, input_adc0, target, input_adc1);
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@@ -109,10 +109,10 @@ static void adc_setup(void)
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static void dac_setup(void)
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{
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gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5);
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dac_disable(CHANNEL_2);
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dac_disable_waveform_generation(CHANNEL_2);
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dac_enable(CHANNEL_2);
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dac_set_trigger_source(DAC_CR_TSEL2_SW);
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dac_disable(DAC1, DAC_CHANNEL2);
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dac_disable_waveform_generation(DAC1, DAC_CHANNEL2);
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dac_enable(DAC1, DAC_CHANNEL2);
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dac_set_trigger_source(DAC1, DAC_CR_TSEL2_SW);
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}
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static uint16_t read_adc_naiive(uint8_t channel)
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@@ -143,8 +143,8 @@ int main(void)
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while (1) {
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uint16_t input_adc0 = read_adc_naiive(0);
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uint16_t target = input_adc0 / 2;
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dac_load_data_buffer_single(target, RIGHT12, CHANNEL_2);
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dac_software_trigger(CHANNEL_2);
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dac_load_data_buffer_single(DAC1, target, DAC_ALIGN_RIGHT12, DAC_CHANNEL2);
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dac_software_trigger(DAC1, DAC_CHANNEL2);
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uint16_t input_adc1 = read_adc_naiive(1);
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printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n",
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j++, input_adc0, target, input_adc1);
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@@ -91,7 +91,7 @@ static void dma_setup(void)
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DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
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/* The register to target is the DAC1 8-bit right justified data
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register */
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dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1);
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dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1(DAC1));
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/* The array v[] is filled with the waveform data to be output */
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dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform);
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dma_set_number_of_data(DMA1, DMA_STREAM5, 256);
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@@ -107,10 +107,10 @@ static void dac_setup(void)
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rcc_periph_clock_enable(RCC_DAC);
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/* Setup the DAC channel 1, with timer 2 as trigger source.
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* Assume the DAC has woken up by the time the first transfer occurs */
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dac_trigger_enable(CHANNEL_1);
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dac_set_trigger_source(DAC_CR_TSEL1_T2);
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dac_dma_enable(CHANNEL_1);
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dac_enable(CHANNEL_1);
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dac_trigger_enable(DAC1, DAC_CHANNEL1);
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dac_set_trigger_source(DAC1, DAC_CR_TSEL1_T2);
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dac_dma_enable(DAC1, DAC_CHANNEL1);
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dac_enable(DAC1, DAC_CHANNEL1);
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}
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/*--------------------------------------------------------------------*/
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@@ -110,10 +110,10 @@ static void adc_setup(void)
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static void dac_setup(void)
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{
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gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5);
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dac_disable(CHANNEL_2);
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dac_disable_waveform_generation(CHANNEL_2);
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dac_enable(CHANNEL_2);
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dac_set_trigger_source(DAC_CR_TSEL2_SW);
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dac_disable(DAC1, DAC_CHANNEL2);
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dac_disable_waveform_generation(DAC1, DAC_CHANNEL2);
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dac_enable(DAC1, DAC_CHANNEL2);
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dac_set_trigger_source(DAC1, DAC_CR_TSEL2_SW);
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}
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static uint16_t read_adc_naiive(uint8_t channel)
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@@ -144,8 +144,8 @@ int main(void)
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while (1) {
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uint16_t input_adc0 = read_adc_naiive(0);
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uint16_t target = input_adc0 / 2;
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dac_load_data_buffer_single(target, RIGHT12, CHANNEL_2);
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dac_software_trigger(CHANNEL_2);
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dac_load_data_buffer_single(DAC1, target, DAC_ALIGN_RIGHT12, DAC_CHANNEL2);
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dac_software_trigger(DAC1, DAC_CHANNEL2);
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uint16_t input_adc1 = read_adc_naiive(1);
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printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n",
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j++, input_adc0, target, input_adc1);
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@@ -92,7 +92,7 @@ static void dma_setup(void)
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DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
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/* The register to target is the DAC1 8-bit right justified data
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register */
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dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1);
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dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1(DAC1));
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/* The array v[] is filled with the waveform data to be output */
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dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform);
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dma_set_number_of_data(DMA1, DMA_STREAM5, 256);
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@@ -108,10 +108,10 @@ static void dac_setup(void)
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rcc_periph_clock_enable(RCC_DAC);
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/* Setup the DAC channel 1, with timer 2 as trigger source.
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* Assume the DAC has woken up by the time the first transfer occurs */
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dac_trigger_enable(CHANNEL_1);
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dac_set_trigger_source(DAC_CR_TSEL1_T2);
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dac_dma_enable(CHANNEL_1);
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dac_enable(CHANNEL_1);
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dac_trigger_enable(DAC1, DAC_CHANNEL1);
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dac_set_trigger_source(DAC1, DAC_CR_TSEL1_T2);
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dac_dma_enable(DAC1, DAC_CHANNEL1);
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dac_enable(DAC1, DAC_CHANNEL1);
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}
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/*--------------------------------------------------------------------*/
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