EMTime/libopencm3-examples
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[rcc_periph_clock_enable] Using the new rcc enable format.

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We are missing handling of stm32l1 AHBLP clock rail.
This commit is contained in:
Piotr Esden-Tempski
2015-01-20 15:33:00 -08:00
parent 1c4ae95729
commit 2583cc54cc
4 changed files with 16 additions and 15 deletions
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8
examples/stm32/l1/stm32l-discovery/lcd-display/lcd-hello.c
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@@ -24,8 +24,9 @@
static void lcd_init(void)
{
/* Move all needed GPIO pins to LCD alternative mode */
rcc_peripheral_enable_clock (&RCC_AHBENR, RCC_AHBENR_GPIOAEN
| RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN);
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
rcc_peripheral_enable_clock (&RCC_AHBLPENR, RCC_AHBLPENR_GPIOALPEN
| RCC_AHBLPENR_GPIOBLPEN | RCC_AHBLPENR_GPIOCLPEN);
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO1 | GPIO2
@@ -45,7 +46,8 @@ static void lcd_init(void)
| GPIO7 | GPIO8 | GPIO9 | GPIO10 | GPIO11);
/* Enable LCD and use LSE clock as RTC/LCD clock. */
rcc_peripheral_enable_clock (&RCC_APB1ENR, RCC_APB1ENR_PWREN | RCC_APB1ENR_LCDEN);
rcc_periph_clock_enable(RCC_PWR);
rcc_periph_clock_enable(RCC_LCD);
pwr_disable_backup_domain_write_protect ();
rcc_osc_on (LSE);
rcc_wait_for_osc_ready (LSE);