[rcc_periph_clock_enable] Using the new rcc enable format.
We are missing handling of stm32l1 AHBLP clock rail.
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@@ -106,8 +106,8 @@ int main(void)
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{
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rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]);
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rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN);
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rcc_peripheral_enable_clock(&RCC_AHB2ENR, RCC_AHB2ENR_OTGFSEN);
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rcc_periph_clock_enable(RCC_GPIOA);
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rcc_periph_clock_enable(RCC_OTGFS);
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE,
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GPIO9 | GPIO11 | GPIO12);
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@@ -107,8 +107,8 @@ int main(void)
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{
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rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]);
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rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPBEN);
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rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_OTGHSEN);
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rcc_periph_clock_enable(RCC_GPIOB);
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rcc_periph_clock_enable(RCC_OTGHS);
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gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE,
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GPIO13 | GPIO14 | GPIO15);
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