[rcc_periph_clock_enable] Using the new rcc enable format.

We are missing handling of stm32l1 AHBLP clock rail.
This commit is contained in:
Piotr Esden-Tempski
2015-01-20 15:33:00 -08:00
parent 1c4ae95729
commit 2583cc54cc
4 changed files with 16 additions and 15 deletions

View File

@@ -106,8 +106,8 @@ int main(void)
{
rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN);
rcc_peripheral_enable_clock(&RCC_AHB2ENR, RCC_AHB2ENR_OTGFSEN);
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_OTGFS);
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE,
GPIO9 | GPIO11 | GPIO12);

View File

@@ -107,8 +107,8 @@ int main(void)
{
rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPBEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_OTGHSEN);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_OTGHS);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE,
GPIO13 | GPIO14 | GPIO15);