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[rcc_periph_clock_enable] Using the new rcc enable format.

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We are missing handling of stm32l1 AHBLP clock rail.
This commit is contained in:
Piotr Esden-Tempski
2015-01-20 15:33:00 -08:00
parent 1c4ae95729
commit 2583cc54cc
4 changed files with 16 additions and 15 deletions
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15
examples/stm32/f1/stm32vl-discovery/spi/spi.c
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@@ -33,18 +33,17 @@ static void clock_setup(void)
rcc_clock_setup_in_hse_8mhz_out_24mhz();
/* Enable GPIOA, GPIOB, GPIOC clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR,
RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN);
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
/* Enable clocks for GPIO port A (for GPIO_USART2_TX) and USART2. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN |
RCC_APB2ENR_AFIOEN);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_AFIO);
rcc_periph_clock_enable(RCC_USART2);
/* Enable SPI1 Periph and gpio clocks */
rcc_peripheral_enable_clock(&RCC_APB2ENR,
RCC_APB2ENR_SPI1EN);
rcc_periph_clock_enable(RCC_SPI1);
}