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Additional cleanup on lcd-serial

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Remove the ISR function and remains of the hack in lcd-spi.c and
convert console.c to use the LOC3 system reset code rather than
the hack which only works on the F4 as it turns out.
This commit is contained in:
Chuck McManis
2015-01-26 14:44:10 -08:00
committed by Piotr Esden-Tempski
parent 5379525a87
commit 0a863789b0
2 changed files with 3 additions and 45 deletions
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28
examples/stm32/f4/stm32f429i-discovery/lcd-serial/lcd-spi.c
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@@ -35,30 +35,6 @@
static int print_decimal(int v);
static int print_hex(int v);
/*
* This is an ungainly workaround (aka hack) basically I want to know
* when the SPI port is 'done' sending all of the bits out, and it is
* done when it has clocked enough bits that it would have received a
* byte. Since we're using the SPI port in write_only mode I am not
* collecting the "received" bytes into a buffer, but one could of
* course. I keep track of how many bytes should have been returned
* by decrementing the 'rx_pend' volatile. When it reaches 0 we know
* we are done.
*/
volatile int rx_pend;
volatile uint16_t spi_rx_buf;
/*
* This is the ISR we use. Note that the name is based on the name
* in the irq.json file of libopencm3 plus the "_isr" extension.
*/
void
spi5_isr(void) {
spi_rx_buf = SPI_DR(SPI5);
--rx_pend;
}
/* Simple double buffering, one frame is displayed, the
* other being built.
*/
@@ -343,10 +319,6 @@ lcd_spi_init(void) {
cur_frame = (uint16_t *)(SDRAM_BASE_ADDRESS);
display_frame = cur_frame + (LCD_WIDTH * LCD_HEIGHT);
rx_pend = 0;
/* Implement state management hack */
// nvic_enable_irq(NVIC_SPI5_IRQ);
rcc_periph_clock_enable(RCC_SPI5);
spi_init_master(LCD_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_4,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,