From 0a863789b04ccea6170bcff2a27649fe30aa7220 Mon Sep 17 00:00:00 2001 From: Chuck McManis Date: Mon, 26 Jan 2015 14:44:10 -0800 Subject: [PATCH] Additional cleanup on lcd-serial Remove the ISR function and remains of the hack in lcd-spi.c and convert console.c to use the LOC3 system reset code rather than the hack which only works on the F4 as it turns out. --- .../stm32f429i-discovery/lcd-serial/console.c | 20 ++----------- .../stm32f429i-discovery/lcd-serial/lcd-spi.c | 28 ------------------- 2 files changed, 3 insertions(+), 45 deletions(-) diff --git a/examples/stm32/f4/stm32f429i-discovery/lcd-serial/console.c b/examples/stm32/f4/stm32f429i-discovery/lcd-serial/console.c index 17cef99..2fdb3d2 100644 --- a/examples/stm32/f4/stm32f429i-discovery/lcd-serial/console.c +++ b/examples/stm32/f4/stm32f429i-discovery/lcd-serial/console.c @@ -68,23 +68,9 @@ void usart1_isr(void) { #ifdef RESET_ON_CTRLC /* Check for "reset" */ if (recv_buf[recv_ndx_nxt] == '\003') { - /* reset the system - * volatile definition of return address on the stack - * to insure it gets stored, changed to point to - * the trampoline function (do_the_nasty) which is - * required because we need to return of an interrupt - * to get the internal value of the LR register reset - * and put the processor back into "Thread" mode from - * "Handler" mode. - * - * See the PM0214 Programming Manual for Cortex M, - * pg 42, to see the format of the Cortex M4 stack after - * an interrupt or exception has occurred. - */ - volatile uint32_t *ret = (®) + 7; - - *ret = (uint32_t) &reset_handler; - return; + /* reset the system */ + scb_reset_system(); + return; /* not reached */ } #endif /* Check for "overrun" */ diff --git a/examples/stm32/f4/stm32f429i-discovery/lcd-serial/lcd-spi.c b/examples/stm32/f4/stm32f429i-discovery/lcd-serial/lcd-spi.c index 0860d18..1c86d3a 100644 --- a/examples/stm32/f4/stm32f429i-discovery/lcd-serial/lcd-spi.c +++ b/examples/stm32/f4/stm32f429i-discovery/lcd-serial/lcd-spi.c @@ -35,30 +35,6 @@ static int print_decimal(int v); static int print_hex(int v); -/* - * This is an ungainly workaround (aka hack) basically I want to know - * when the SPI port is 'done' sending all of the bits out, and it is - * done when it has clocked enough bits that it would have received a - * byte. Since we're using the SPI port in write_only mode I am not - * collecting the "received" bytes into a buffer, but one could of - * course. I keep track of how many bytes should have been returned - * by decrementing the 'rx_pend' volatile. When it reaches 0 we know - * we are done. - */ - -volatile int rx_pend; -volatile uint16_t spi_rx_buf; - -/* - * This is the ISR we use. Note that the name is based on the name - * in the irq.json file of libopencm3 plus the "_isr" extension. - */ -void -spi5_isr(void) { - spi_rx_buf = SPI_DR(SPI5); - --rx_pend; -} - /* Simple double buffering, one frame is displayed, the * other being built. */ @@ -343,10 +319,6 @@ lcd_spi_init(void) { cur_frame = (uint16_t *)(SDRAM_BASE_ADDRESS); display_frame = cur_frame + (LCD_WIDTH * LCD_HEIGHT); - rx_pend = 0; - /* Implement state management hack */ - // nvic_enable_irq(NVIC_SPI5_IRQ); - rcc_periph_clock_enable(RCC_SPI5); spi_init_master(LCD_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,