diff --git a/1gpio/bin/gpio.bin b/1gpio/bin/gpio.bin new file mode 100755 index 0000000..61bda58 Binary files /dev/null and b/1gpio/bin/gpio.bin differ diff --git a/1gpio/bin/gpio.elf b/1gpio/bin/gpio.elf new file mode 100755 index 0000000..407bc5b Binary files /dev/null and b/1gpio/bin/gpio.elf differ diff --git a/1gpio/bin/gpio.hex b/1gpio/bin/gpio.hex new file mode 100644 index 0000000..40caf3d --- /dev/null +++ b/1gpio/bin/gpio.hex @@ -0,0 +1,218 @@ +:020000040800F2 +:1000000000000220BD090008B9090008B70900086E +:10001000B7090008B7090008B70900080000000088 +:10002000000000000000000000000000B909000806 +:10003000B909000800000000B9090008C904000857 +:10004000B7090008B7090008B7090008B709000890 +:10005000B7090008B7090008B7090008B709000880 +:10006000B7090008B7090008B7090008B709000870 +:10007000B7090008B7090008B7090008B709000860 +:10008000B7090008B7090008B7090008B709000850 +:10009000B7090008B7090008B7090008B709000840 +:1000A000B7090008B7090008B7090008B709000830 +:1000B000B7090008B7090008B7090008B709000820 +:1000C000B7090008B7090008B7090008B709000810 +:1000D000B7090008B7090008B7090008B709000800 +:1000E000B7090008B7090008B7090008B7090008F0 +:1000F000B7090008B7090008B7090008B7090008E0 +:10010000B7090008B7090008B7090008B7090008CF +:10011000B7090008B7090008B7090008B7090008BF +:10012000B7090008B7090008B7090008B7090008AF +:10013000B7090008B7090008B7090008B70900089F +:10014000B7090008B7090008B7090008B70900088F +:10015000B7090008B7090008B7090008B70900087F +:10016000B7090008B7090008B7090008B70900086F +:10017000B7090008B7090008B7090008B70900085F +:10018000B7090008B7090008B7090008B70900084F +:10019000B7090008B7090008B7090008B70900083F +:1001A000B7090008B7090008B7090008B70900082F +:1001B000B7090008B7090008B7090008B70900081F +:1001C000B7090008B7090008B7090008B70900080F +:1001D000B7090008B7090008B7090008B7090008FF +:1001E000B7090008B7090008B7090008B7090008EF +:1001F000B7090008B7090008B7090008B7090008DF +:10020000B7090008B7090008B7090008B7090008CE +:10021000B7090008B7090008B7090008B7090008BE +:10022000B7090008B7090008B7090008B7090008AE +:10023000B7090008B7090008B7090008B70900089E +:10024000B7090008B7090008B7090008B70900088E +:10025000B7090008B7090008B7090008B70900087E +:10026000B7090008B7090008B7090008B70900086E +:10027000B7090008B7090008B7090008B70900085E +:10028000B7090008B7090008B7090008B70900084E +:10029000B7090008B709000880B500AF41F604406F +:1002A00000F07CFB082300220121104800F02BF90C +:1002B0000823002200210D4800F045F908210B48D1 +:1002C00000F012F90A4B1B68094A43F4807313606B +:1002D00041F6024000F062FB4FF40053022200217D +:1002E000044800F010F900BF80BD00BF00100258A4 +:1002F000004802580008025880B500AF4FF4407023 +:1003000000F0CFFB00F02CF84FF47A7000F0BCF84E +:10031000FFF7C2FF4FF400510F4800F0E8F8034622 +:10032000002BF7D0142000F095F84FF400510A4844 +:1003300000F0DDF80346002B03D00821074800F049 +:10034000D9F800BF4FF40051034800F0D0F803463D +:10035000002BF7D1DEE700BF00080258001002585A +:1003600080B58CB000AF3B462C220021184600F02F +:1003700091FC41F6074000F011FB41F6816000F06E +:100380000DFB022301220121304800F0BCF80223BA +:10039000022200212D4800F0D6F80023FB6203E082 +:1003A00000BFFB6A0133FB62FB6A132BF8D9022101 +:1003B000264800F097F800233B7002237B70244B03 +:1003C0007B6005233B72C0237B8102233B730223A6 +:1003D0007B730223BB7320233B7481237B82022324 +:1003E0003B7502237B750223BB7520233B7681235B +:1003F0007B8302233B7702237B770223BB77002397 +:1004000087F82030082387F82130042387F822302A +:10041000042387F82330042387F82430042387F843 +:100420002530042387F82630012387F8273002235C +:1004300087F82830002387F829303B46184600F01B +:1004400063F900BF3037BD4680BD00BF001C0258B5 +:1004500040787D0180B485B000AF7860094B1B689F +:10046000FB6001E030BF00BF064B1A68FB68D31A7F +:100470007A689A42F6D800BF00BF1437BD465DF8CF +:10048000047B70472400002080B582B000AF786004 +:10049000042000F0E9FA002000F042FA02467B68EE +:1004A000B2FBF3F3013B184600F0D8FA00F0F4FA7F +:1004B0000F21FF2000F0FEFA00F0E0FA00F0E5FA6C +:1004C00000BF0837BD4680BD80B400AF044B1B6839 +:1004D0000133034A136000BFBD465DF8047B7047DB +:1004E0002400002081617047090481617047006920 +:1004F00008407047436901EA030221EA030141EA27 +:100500000241816170472DE9F04105680026C46809 +:100510004FF0030E43FA06F7FF070DD577000EFAEA +:1005200007FC01FA07F802FA07F725EA0C0524EAA6 +:100530000C0448EA05053C430136102EEAD105605B +:10054000C460BDE8F081012941680CBF194399439B +:10055000F0B5416000248168032643FA04F5ED07F5 +:1005600007D5650006FA05F702FA05F521EA070145 +:1005700029430134102CF0D18160F0BD2DE9F04306 +:1005800091F800C0BCF1000F00F0A580012A26D030 +:10059000574B9E1F022A18BF1E46013A554D002395 +:1005A000B1F8028045F8323008F1FF3355F8324097 +:1005B0002343D4B245F83230A700B0FBFCF34E48D9 +:1005C000FFB2B3FBF0FCACF1030001284B4808D8A4 +:1005D0000423D0F82CE4BB404EEA03030DE0484E60 +:1005E000DBE7ACF1050EBEF1030F76D80823D0F897 +:1005F0002C9403FA07FE4EEA0903C0F82C340CFBD6 +:1006000008F3B3F5D27F09D8DFF8F0C00220DCF898 +:100610002CE4B84040EA0E00CCF82C0467000879BE +:1006200004EB4404E4B2B0B155F832C000F1FF3E2F +:100630004CEA4E2CDFF8C4E045F832C04FF4803C61 +:10064000DEF82C840CFA04FCB3FBF0F04CEA080C46 +:10065000CEF82CC430804879B0B155F832C000F1E2 +:10066000FF3E4CEA0E4CDFF894E045F832C04FF400 +:10067000003CDEF82C840CFA04FCB3FBF0F04CEAEE +:10068000080CCEF82CC47080897999B155F83200E5 +:1006900001F1FF3C40EA0C6045F832004FF4802243 +:1006A0001648A240D0F82C54B3FBF1F32A43C0F80B +:1006B0002C24B380114AFFB24FF08073D2F800149B +:1006C000BB400B43C2F800344FF00073BB40D2F87C +:1006D00000141942FBD0BDE8F083DFF828E0734531 +:1006E0008DD94FF00C0ED0F82C340EFA07FE73E7BC +:1006F0001A0000203044025840420F0000400258C7 +:100700000E0000203F548900F8B5814B0446D3F811 +:10071000002442F00102C3F80024D3F8102422F090 +:100720000702C3F81024D3F8102412F0380FFAD1BE +:100730000122C3F8002494F8291094F8280000F04E +:100740002FFA94F8270000F057FA94F8260000F0EA +:10075000D3F994F82630002B00F0C58000F0BCF9E6 +:1007600063688BB16A4BD3F8002442F48032C3F83B +:100770000024D3F800249203FBD563684FF47A7207 +:10078000B3FBF2F3634A1384237C227A1B03617860 +:1007900043EA0213227E0B4343EA02535C4AC2F847 +:1007A0002834002900F0A2806568002304F10801C4 +:1007B0002846C2F82C340122FFF7E0FE022204F1A1 +:1007C00010012846FFF7DAFE2846032204F118013B +:1007D000FFF7D4FE23784F48002B40F08980C3896F +:1007E00094F8245000264A4F94F8201094F82120C1 +:1007F00003800729C7F818644FEA0516D7F818C40C +:1008000046EA012646EA020646EA0C06C7F81864DC +:1008100006D90B2994BF0739063943FA01F18BB287 +:10082000072A438009D90B2A95BF073A911F43FA3B +:1008300002F20B4194BF93B29BB2032D94F82310A4 +:10084000334E8CBFEA1E1A464FF00005838084BFEA +:1008500043FA02F292B20329428194F82220C6F8A8 +:100860001C544FEA01258CBF0339194645EA02158D +:10087000D6F81C7488BF43FA01F145EA070588BF22 +:1008800089B2032AC6F81C548CBF033A1A46018168 +:1008900088BF43FA02F294F8251088BF92B2032968 +:1008A000C2801B4AD2F820444FF00004C2F8204412 +:1008B000D2F8204444EA011484BF033943FA01F119 +:1008C000C2F8204488BF8BB28381D2F8103443F041 +:1008D0000303C2F81034D2F810340D4AC3F3C20334 +:1008E000032B0FD1F8BD00F0FFF839E70A4D5CE7A4 +:1008F000012B09BF63684023084AB3FBF2F308BF2A +:100900009BB26DE7D2F81034C3F3C203E8E700BF2F +:1009100000400258000000200090D00340420F0029 +:1009200008B509282CD8DFE800F00A051C0A0D0DCF +:1009300010131619154B1888154B584308BD134B47 +:100940005888F9E7114B9888F6E7104BD888F3E7F9 +:100950000E4B1889F0E70D4B5889EDE70B4B988942 +:10096000EAE70C4BD3F84C3413F0405FC3F3017249 +:1009700008D0022A08D1054B188C4FF47A73DCE7B3 +:1009800000F0A8F80448D9E70020D7E700000020CD +:1009900040420F00004002580090D003430901225A +:1009A00000F01F0003F1B043824003F511331968D2 +:1009B0000A431A607047FEE77047000038B51D4AC9 +:1009C0001D4B1E498B4220D31D4A0021934221D347 +:1009D0004FF0E0231B4C1C4DD3F8142D42F4007251 +:1009E000C3F8142DD3F8882D42F47002C3F8882D73 +:1009F000AC4212D3154C164DAC4212D3154CFFF736 +:100A00007BFC154DAC4210D338BD52F8040B43F8B3 +:100A1000040BD7E743F8041BD8E754F8043B984786 +:100A2000E6E754F8043B9847E6E754F8043B984758 +:100A3000E8E700BF380D0008000000202400002077 +:100A400028000020380D0008380D0008380D000877 +:100A5000380D0008380D0008380D000820F07F40E0 +:100A60004FF0E023586170474FF0E02200F004009F +:100A7000136923F004030343136170474FF0E0222E +:100A8000136943F00203136170474FF0E0221369CA +:100A900043F00103136170474FF0E02300229A6195 +:100AA000704740F0BF604FF0E02340F40030C3F8DF +:100AB0000C0D7047952804D900F00F00044BC15469 +:100AC000704700F1604000F564400170704700BF5E +:100AD00014ED00E0FEE70000024A136843F480735F +:100AE0001360704700200052024A136823F4807399 +:100AF0001360704700200052034A136823F00F036D +:100B000003431360704700BF00200052044AD2F82C +:100B10000C3823F0070343F00203C2F80C38704787 +:100B200000400258044AD2F80C3823F0070343F07F +:100B30000603C2F80C3870470040025808B50B0194 +:100B400070B943F0040309485242D0F80C1802F07F +:100B5000020221F03F010A431A43C0F80C2808BDE5 +:100B600009B9FFF7B7FF43F00C03ECE70040025868 +:100B7000044AD2F80C3823F0070343F00103C2F80B +:100B80000C38704700400258044AD2F80C3823F061 +:100B9000070343F00503C2F80C38704700400258C1 +:100BA00008B5072807D8DFE800F0040C0F12121D63 +:100BB0001D21FFF7B7FF0F4AD2F804389B04FBD57D +:100BC00008BDFFF7E1FFF6E7FFF7A0FFF3E7A0F1AD +:100BD000040C0021DCF1000242EB0C020020FFF7C4 +:100BE000ADFFE8E7053842424241F7E7FFF7C0FFB3 +:100BF000E1E700BF00400258F8B5074608B9FFF723 +:100C000069FF204B421E204E1B68C3F30B03B3F554 +:100C1000906F0FD1D6F818381C4923F440438A5CF2 +:100C200043EA8233C6F81838174AD2F818389B04BA +:100C3000FBD5F8BD1649B3F58A6FD6F818588C5C09 +:100C400025F440454FEA843418D141F68160FFF71E +:100C5000A5FE012F4FF0B0430AD145F44045C6F838 +:100C60001858D3F82C2442F00102C3F82C24DBE7F7 +:100C7000D3F82C2422F00102C3F82C242C43C6F80C +:100C80001848D1E70010005C00400258340D0008FD +:100C9000300D0008830730B546D08418844604E040 +:100CA00003F8011B9D0704D09C46A4456346F7D179 +:100CB00030BD013A0244A2EB0C02032A29D9CCB27E +:100CC00004EB04240F2A04EB04442FD9A2F1100CE6 +:100CD0002CF00F0C03F11005AC44C3E90044C3E948 +:100CE000024410336345F8D112F00C0F02F00F0EDE +:100CF00018D02EF0030C9C44AEF104051A4642F8BD +:100D0000044B6245FBD125F0030404330EF00302CB +:100D10002344002ACCD0C9B21A4403F8011B9342E1 +:100D2000FBD130BD7246F4E70346C6E79646E0E7DE +:080D30000003020103020100AF +:100D380040004000400040004000400040000000EB +:100D4800000000000000000000000000000000009B +:040D58000000000097 +:04000005080009BD29 +:00000001FF diff --git a/1gpio/bin/gpio.list b/1gpio/bin/gpio.list new file mode 100755 index 0000000..a9916e7 --- /dev/null +++ b/1gpio/bin/gpio.list @@ -0,0 +1,1902 @@ + +/home/time/doc/codefile/embe/Blog/stm32/stm32h7/1gpio/bin/gpio.elf: file format elf32-littlearm + + +Disassembly of section .text: + +08000000 : + 8000000: 00 00 02 20 bd 09 00 08 b9 09 00 08 b7 09 00 08 ... ............ + 8000010: b7 09 00 08 b7 09 00 08 b7 09 00 08 00 00 00 00 ................ + ... + 800002c: b9 09 00 08 b9 09 00 08 00 00 00 00 b9 09 00 08 ................ + 800003c: c9 04 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800004c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800005c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800006c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800007c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800008c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800009c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80000ac: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80000bc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80000cc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80000dc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80000ec: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80000fc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800010c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800011c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800012c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800013c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800014c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800015c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800016c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800017c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800018c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800019c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80001ac: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80001bc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80001cc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80001dc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80001ec: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 80001fc: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800020c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800021c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800022c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800023c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800024c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800025c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800026c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800027c: b7 09 00 08 b7 09 00 08 b7 09 00 08 b7 09 00 08 ................ + 800028c: b7 09 00 08 b7 09 00 08 b7 09 00 08 ............ + +08000298 : + * 在多任务系统中,如果多个任务访问同一GPIO,可能需要添加同步机制。 + * + * @see rcc_periph_clock_enable(), gpio_mode_setup(), gpio_set_output_options(), gpio_clear() + */ +void user_gpio_setup(void) +{ + 8000298: b580 push {r7, lr} + 800029a: af00 add r7, sp, #0 + // 使能GPIOE端口的时钟,必须先使能时钟才能配置和使用该端口的引脚 + rcc_periph_clock_enable(RCC_GPIOE); + 800029c: f641 4004 movw r0, #7172 @ 0x1c04 + 80002a0: f000 fb7c bl 800099c + + // 配置GPIOE端口的引脚3为输出模式,不使用上拉或下拉电阻 + gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3); + 80002a4: 2308 movs r3, #8 + 80002a6: 2200 movs r2, #0 + 80002a8: 2101 movs r1, #1 + 80002aa: 4810 ldr r0, [pc, #64] @ (80002ec ) + 80002ac: f000 f92b bl 8000506 + + // 设置GPIOE端口引脚3的输出选项：推挽输出类型,速度为2MHz + gpio_set_output_options(GPIOE, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, GPIO3); + 80002b0: 2308 movs r3, #8 + 80002b2: 2200 movs r2, #0 + 80002b4: 2100 movs r1, #0 + 80002b6: 480d ldr r0, [pc, #52] @ (80002ec ) + 80002b8: f000 f945 bl 8000546 + + // 将GPIOE端口引脚3设置为低电平,也就是灯灭 + gpio_clear(GPIOE, GPIO3); + 80002bc: 2108 movs r1, #8 + 80002be: 480b ldr r0, [pc, #44] @ (80002ec ) + 80002c0: f000 f912 bl 80004e8 + + // 使能备份域访问,通过设置电源控制寄存器1的DBP位 + // 这是访问RTC、备份寄存器等备份域外设的必要步骤 + // PC13-PC15是备份域的GPIO引脚,需要使能备份域访问才能配置这些引脚 + PWR_CR1 |= PWR_CR1_DBP; + 80002c4: 4b0a ldr r3, [pc, #40] @ (80002f0 ) + 80002c6: 681b ldr r3, [r3, #0] + 80002c8: 4a09 ldr r2, [pc, #36] @ (80002f0 ) + 80002ca: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80002ce: 6013 str r3, [r2, #0] + + // 使能GPIOC端口的时钟,必须先使能时钟才能配置和使用该端口的引脚 + rcc_periph_clock_enable(RCC_GPIOC); + 80002d0: f641 4002 movw r0, #7170 @ 0x1c02 + 80002d4: f000 fb62 bl 800099c + + // 配置GPIOC端口的引脚13为输入模式,并启用下拉电阻 + gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO13); + 80002d8: f44f 5300 mov.w r3, #8192 @ 0x2000 + 80002dc: 2202 movs r2, #2 + 80002de: 2100 movs r1, #0 + 80002e0: 4804 ldr r0, [pc, #16] @ (80002f4 ) + 80002e2: f000 f910 bl 8000506 +} + 80002e6: bf00 nop + 80002e8: bd80 pop {r7, pc} + 80002ea: bf00 nop + 80002ec: 58021000 .word 0x58021000 + 80002f0: 58024800 .word 0x58024800 + 80002f4: 58020800 .word 0x58020800 + +080002f8
: + * + * @see scb_set_priority_grouping(), system_clock_setup(), systick_init(), + * user_gpio_setup(), user_delay_ms(), gpio_get(), gpio_toggle() + */ +int main(void) +{ + 80002f8: b580 push {r7, lr} + 80002fa: af00 add r7, sp, #0 + // 设置中断优先级分组为16个主优先级,无子优先级 + // 这意味着每个中断都有独立的优先级,没有子优先级用于同一优先级中断的排序 + scb_set_priority_grouping(SCB_AIRCR_PRIGROUP_GROUP16_NOSUB); + 80002fc: f44f 7040 mov.w r0, #768 @ 0x300 + 8000300: f000 fbcf bl 8000aa2 + + // 初始化系统时钟配置 + system_clock_setup(); + 8000304: f000 f82c bl 8000360 + + // 初始化SysTick定时器,参数1000U表示每秒产生1000次中断,即每1ms一次 + systick_init(1000U); + 8000308: f44f 707a mov.w r0, #1000 @ 0x3e8 + 800030c: f000 f8bc bl 8000488 + + // 初始化用户GPIO引脚配置 + // 根据gpio的代码,这包括配置PE3为输出（LED）和PC13为输入（按钮） + user_gpio_setup(); + 8000310: f7ff ffc2 bl 8000298 + + // 主循环,程序将在此无限循环 + while (1) + { + // 检测PC13引脚（按钮）的状态,如果为高电平（按钮按下）则执行以下代码 + if(gpio_get(GPIOC, GPIO13)) + 8000314: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8000318: 480f ldr r0, [pc, #60] @ (8000358 ) + 800031a: f000 f8e8 bl 80004ee + 800031e: 4603 mov r3, r0 + 8000320: 2b00 cmp r3, #0 + 8000322: d0f7 beq.n 8000314 + { + // 延时20ms,用于按钮消抖 + // 按钮在按下和释放时会产生机械抖动,延时可以避免误检测 + user_delay_ms(20); + 8000324: 2014 movs r0, #20 + 8000326: f000 f895 bl 8000454 + + // 再次检测按钮状态,确认按钮确实被按下（不是抖动） + if(gpio_get(GPIOC, GPIO13)) + 800032a: f44f 5100 mov.w r1, #8192 @ 0x2000 + 800032e: 480a ldr r0, [pc, #40] @ (8000358 ) + 8000330: f000 f8dd bl 80004ee + 8000334: 4603 mov r3, r0 + 8000336: 2b00 cmp r3, #0 + 8000338: d003 beq.n 8000342 + { + // 切换PE3引脚（LED）的状态 + // 如果LED当前是亮的状态,则熄灭；如果是灭的状态,则点亮 + gpio_toggle(GPIOE, GPIO3); + 800033a: 2108 movs r1, #8 + 800033c: 4807 ldr r0, [pc, #28] @ (800035c ) + 800033e: f000 f8d9 bl 80004f4 + } + + // 等待按钮释放 + // 这是一个空循环,一直检测直到按钮被释放（PC13变为低电平） + // 这样可以防止在按钮按住期间多次触发LED切换 + while(gpio_get(GPIOC, GPIO13)); + 8000342: bf00 nop + 8000344: f44f 5100 mov.w r1, #8192 @ 0x2000 + 8000348: 4803 ldr r0, [pc, #12] @ (8000358 ) + 800034a: f000 f8d0 bl 80004ee + 800034e: 4603 mov r3, r0 + 8000350: 2b00 cmp r3, #0 + 8000352: d1f7 bne.n 8000344 + if(gpio_get(GPIOC, GPIO13)) + 8000354: e7de b.n 8000314 + 8000356: bf00 nop + 8000358: 58020800 .word 0x58020800 + 800035c: 58021000 .word 0x58021000 + +08000360 : + * + * @see rcc_periph_clock_enable(), gpio_mode_setup(), gpio_set_output_options(), + * gpio_set(), rcc_clock_setup_pll() + */ +static void system_clock_setup(void) +{ + 8000360: b580 push {r7, lr} + 8000362: b08c sub sp, #48 @ 0x30 + 8000364: af00 add r7, sp, #0 + // 初始化PLL配置结构体,所有成员清零 + struct rcc_pll_config pll_config = {0}; + 8000366: 463b mov r3, r7 + 8000368: 222c movs r2, #44 @ 0x2c + 800036a: 2100 movs r1, #0 + 800036c: 4618 mov r0, r3 + 800036e: f000 fc91 bl 8000c94 + + // 使能GPIOH端口时钟,用于配置GPIOH1引脚 + // OSC_IN是GPIOH0,OSC_OUT是GPIOH1 + rcc_periph_clock_enable(RCC_GPIOH); + 8000372: f641 4007 movw r0, #7175 @ 0x1c07 + 8000376: f000 fb11 bl 800099c + // 使能SYSCFG时钟,用于系统配置 + rcc_periph_clock_enable(RCC_SYSCFG); + 800037a: f641 6081 movw r0, #7809 @ 0x1e81 + 800037e: f000 fb0d bl 800099c + + // 配置GPIOH1引脚为输出模式,启用上拉电阻 + gpio_mode_setup(GPIOH, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO1); + 8000382: 2302 movs r3, #2 + 8000384: 2201 movs r2, #1 + 8000386: 2101 movs r1, #1 + 8000388: 4830 ldr r0, [pc, #192] @ (800044c ) + 800038a: f000 f8bc bl 8000506 + // 设置GPIOH1引脚为推挽输出,速度为50MHz + gpio_set_output_options(GPIOH, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO1); + 800038e: 2302 movs r3, #2 + 8000390: 2202 movs r2, #2 + 8000392: 2100 movs r1, #0 + 8000394: 482d ldr r0, [pc, #180] @ (800044c ) + 8000396: f000 f8d6 bl 8000546 + + // 短暂延时,确保GPIO配置稳定 + for (unsigned i = 0; i < 20; i++) + 800039a: 2300 movs r3, #0 + 800039c: 62fb str r3, [r7, #44] @ 0x2c + 800039e: e003 b.n 80003a8 + { + __asm__("nop"); // 空操作指令,用于延时 + 80003a0: bf00 nop + for (unsigned i = 0; i < 20; i++) + 80003a2: 6afb ldr r3, [r7, #44] @ 0x2c + 80003a4: 3301 adds r3, #1 + 80003a6: 62fb str r3, [r7, #44] @ 0x2c + 80003a8: 6afb ldr r3, [r7, #44] @ 0x2c + 80003aa: 2b13 cmp r3, #19 + 80003ac: d9f8 bls.n 80003a0 + } + // 将GPIOH1引脚设置为高电平 + gpio_set(GPIOH, GPIO1); + 80003ae: 2102 movs r1, #2 + 80003b0: 4826 ldr r0, [pc, #152] @ (800044c ) + 80003b2: f000 f897 bl 80004e4 + + // 设置系统时钟源为PLL + pll_config.sysclock_source = RCC_PLL; + 80003b6: 2300 movs r3, #0 + 80003b8: 703b strb r3, [r7, #0] + // 设置PLL时钟源为外部高速晶振(HSE) + pll_config.pll_source = RCC_PLLCKSELR_PLLSRC_HSE; + 80003ba: 2302 movs r3, #2 + 80003bc: 707b strb r3, [r7, #1] + // 设置HSE频率为25MHz + pll_config.hse_frequency = 25000000U; + 80003be: 4b24 ldr r3, [pc, #144] @ (8000450 ) + 80003c0: 607b str r3, [r7, #4] + + // 配置PLL1参数,这一部分可以和CubeMX进行一一对应 + // 系统时钟频率 = HSE / M * N / P = 25MHz / 5 * 192 / 2 = 480MHz + pll_config.pll1.divm = 5; + 80003c2: 2305 movs r3, #5 + 80003c4: 723b strb r3, [r7, #8] + pll_config.pll1.divn = 192; + 80003c6: 23c0 movs r3, #192 @ 0xc0 + 80003c8: 817b strh r3, [r7, #10] + pll_config.pll1.divp = 2; + 80003ca: 2302 movs r3, #2 + 80003cc: 733b strb r3, [r7, #12] + pll_config.pll1.divq = 2; + 80003ce: 2302 movs r3, #2 + 80003d0: 737b strb r3, [r7, #13] + pll_config.pll1.divr = 2; + 80003d2: 2302 movs r3, #2 + 80003d4: 73bb strb r3, [r7, #14] + + // 配置PLL2参数 + pll_config.pll2.divm = 32; + 80003d6: 2320 movs r3, #32 + 80003d8: 743b strb r3, [r7, #16] + pll_config.pll2.divn = 129; + 80003da: 2381 movs r3, #129 @ 0x81 + 80003dc: 827b strh r3, [r7, #18] + pll_config.pll2.divp = 2; + 80003de: 2302 movs r3, #2 + 80003e0: 753b strb r3, [r7, #20] + pll_config.pll2.divq = 2; + 80003e2: 2302 movs r3, #2 + 80003e4: 757b strb r3, [r7, #21] + pll_config.pll2.divr = 2; + 80003e6: 2302 movs r3, #2 + 80003e8: 75bb strb r3, [r7, #22] + + // 配置PLL3参数 + pll_config.pll3.divm = 32; + 80003ea: 2320 movs r3, #32 + 80003ec: 763b strb r3, [r7, #24] + pll_config.pll3.divn = 129; + 80003ee: 2381 movs r3, #129 @ 0x81 + 80003f0: 837b strh r3, [r7, #26] + pll_config.pll3.divp = 2; + 80003f2: 2302 movs r3, #2 + 80003f4: 773b strb r3, [r7, #28] + pll_config.pll3.divq = 2; + 80003f6: 2302 movs r3, #2 + 80003f8: 777b strb r3, [r7, #29] + pll_config.pll3.divr = 2; + 80003fa: 2302 movs r3, #2 + 80003fc: 77bb strb r3, [r7, #30] + + // 配置系统时钟分频参数,还是可以和CubeMX进行一一对应 + pll_config.core_pre = RCC_D1CFGR_D1CPRE_BYP; // CPU核心时钟不分频 + 80003fe: 2300 movs r3, #0 + 8000400: f887 3020 strb.w r3, [r7, #32] + pll_config.hpre = RCC_D1CFGR_D1HPRE_DIV2; // AHB总线时钟2分频 + 8000404: 2308 movs r3, #8 + 8000406: f887 3021 strb.w r3, [r7, #33] @ 0x21 + pll_config.ppre1 = RCC_D2CFGR_D2PPRE_DIV2; // APB1总线时钟2分频 + 800040a: 2304 movs r3, #4 + 800040c: f887 3022 strb.w r3, [r7, #34] @ 0x22 + pll_config.ppre2 = RCC_D2CFGR_D2PPRE_DIV2; // APB2总线时钟2分频 + 8000410: 2304 movs r3, #4 + 8000412: f887 3023 strb.w r3, [r7, #35] @ 0x23 + pll_config.ppre3 = RCC_D1CFGR_D1PPRE_DIV2; // APB3总线时钟2分频 + 8000416: 2304 movs r3, #4 + 8000418: f887 3024 strb.w r3, [r7, #36] @ 0x24 + pll_config.ppre4 = RCC_D3CFGR_D3PPRE_DIV2; // APB4总线时钟2分频 + 800041c: 2304 movs r3, #4 + 800041e: f887 3025 strb.w r3, [r7, #37] @ 0x25 + + // 设置Flash等待状态为4个周期,确保在480MHz系统时钟下能正确访问Flash + pll_config.flash_waitstates = FLASH_ACR_LATENCY_4WS; + 8000422: 2304 movs r3, #4 + 8000424: f887 3026 strb.w r3, [r7, #38] @ 0x26 + + // 配置电压缩放和电源模式 + pll_config.voltage_scale = PWR_VOS_SCALE_0; // 电压缩放级别0,最高性能模式 + 8000428: 2301 movs r3, #1 + 800042a: f887 3027 strb.w r3, [r7, #39] @ 0x27 + pll_config.power_mode = PWR_SYS_LDO; // 使用LDO(低压差线性稳压器)电源模式 + 800042e: 2302 movs r3, #2 + 8000430: f887 3028 strb.w r3, [r7, #40] @ 0x28 + pll_config.smps_level = 0; // SMPS(开关模式电源)级别 + 8000434: 2300 movs r3, #0 + 8000436: f887 3029 strb.w r3, [r7, #41] @ 0x29 + + // 应用PLL配置,完成系统时钟设置 + rcc_clock_setup_pll(&pll_config); + 800043a: 463b mov r3, r7 + 800043c: 4618 mov r0, r3 + 800043e: f000 f963 bl 8000708 +} + 8000442: bf00 nop + 8000444: 3730 adds r7, #48 @ 0x30 + 8000446: 46bd mov sp, r7 + 8000448: bd80 pop {r7, pc} + 800044a: bf00 nop + 800044c: 58021c00 .word 0x58021c00 + 8000450: 017d7840 .word 0x017d7840 + +08000454 : + * 最大延时时间受限于32位无符号整数的最大值(约49.7天)。 + * + * @see systick, __WFI() + */ +void user_delay_ms(uint32_t ms) +{ + 8000454: b480 push {r7} + 8000456: b085 sub sp, #20 + 8000458: af00 add r7, sp, #0 + 800045a: 6078 str r0, [r7, #4] + // 记录开始延时的时刻（systick的当前值） + uint32_t start = systick; + 800045c: 4b09 ldr r3, [pc, #36] @ (8000484 ) + 800045e: 681b ldr r3, [r3, #0] + 8000460: 60fb str r3, [r7, #12] + + // 循环等待,直到经过的时间达到指定的毫秒数 + while (systick - start < ms) + 8000462: e001 b.n 8000468 + __asm volatile("wfi"); + 8000464: bf30 wfi +} + 8000466: bf00 nop + while (systick - start < ms) + 8000468: 4b06 ldr r3, [pc, #24] @ (8000484 ) + 800046a: 681a ldr r2, [r3, #0] + 800046c: 68fb ldr r3, [r7, #12] + 800046e: 1ad3 subs r3, r2, r3 + 8000470: 687a ldr r2, [r7, #4] + 8000472: 429a cmp r2, r3 + 8000474: d8f6 bhi.n 8000464 + { + // 进入低功耗模式,等待中断唤醒,有助于在延时时降低CPU功耗 + __WFI(); + } +} + 8000476: bf00 nop + 8000478: bf00 nop + 800047a: 3714 adds r7, #20 + 800047c: 46bd mov sp, r7 + 800047e: f85d 7b04 ldr.w r7, [sp], #4 + 8000482: 4770 bx lr + 8000484: 20000024 .word 0x20000024 + +08000488 : + * 此函数会覆盖任何之前的SysTick配置,包括中断处理函数的注册。 + * + * @see sys_tick_handler(), systick, user_delay_ms() + */ +void systick_init(uint32_t ticks) +{ + 8000488: b580 push {r7, lr} + 800048a: b082 sub sp, #8 + 800048c: af00 add r7, sp, #0 + 800048e: 6078 str r0, [r7, #4] + // 设置SysTick时钟源为AHB总线时钟 + systick_set_clocksource(STK_CSR_CLKSOURCE_AHB); + 8000490: 2004 movs r0, #4 + 8000492: f000 fae9 bl 8000a68 + + // 计算重载值：总线频率除以定时器周期数减1 + systick_set_reload((rcc_get_bus_clk_freq(RCC_CPUCLK) / ticks) - 1UL); + 8000496: 2000 movs r0, #0 + 8000498: f000 fa42 bl 8000920 + 800049c: 4602 mov r2, r0 + 800049e: 687b ldr r3, [r7, #4] + 80004a0: fbb2 f3f3 udiv r3, r2, r3 + 80004a4: 3b01 subs r3, #1 + 80004a6: 4618 mov r0, r3 + 80004a8: f000 fad8 bl 8000a5c + + // 清除SysTick当前值寄存器（被注释掉的代码） + //STK_CVR = 0UL; + // 使用函数方式清除SysTick计数器 + systick_clear(); + 80004ac: f000 faf4 bl 8000a98 + + // 设置SysTick中断优先级为15（最低优先级） + nvic_set_priority(NVIC_SYSTICK_IRQ, 15); + 80004b0: 210f movs r1, #15 + 80004b2: 20ff movs r0, #255 @ 0xff + 80004b4: f000 fafe bl 8000ab4 + + // 使用函数方式配置SysTick控制寄存器（被注释掉的代码） + // STK_CSR = STK_CSR_CLKSOURCE | STK_CSR_TICKINT | STK_CSR_ENABLE; + // 分别使能SysTick中断和计数器 + systick_interrupt_enable(); + 80004b8: f000 fae0 bl 8000a7c + systick_counter_enable(); + 80004bc: f000 fae5 bl 8000a8a +} + 80004c0: bf00 nop + 80004c2: 3708 adds r7, #8 + 80004c4: 46bd mov sp, r7 + 80004c6: bd80 pop {r7, pc} + +080004c8 : + * 如果systick变量在多线程/多任务环境中被访问,可能需要添加适当的同步机制。 + * + * @see systick, systick_init(), user_delay_ms() + */ +void sys_tick_handler(void) +{ + 80004c8: b480 push {r7} + 80004ca: af00 add r7, sp, #0 + systick++; + 80004cc: 4b04 ldr r3, [pc, #16] @ (80004e0 ) + 80004ce: 681b ldr r3, [r3, #0] + 80004d0: 3301 adds r3, #1 + 80004d2: 4a03 ldr r2, [pc, #12] @ (80004e0 ) + 80004d4: 6013 str r3, [r2, #0] +} + 80004d6: bf00 nop + 80004d8: 46bd mov sp, r7 + 80004da: f85d 7b04 ldr.w r7, [sp], #4 + 80004de: 4770 bx lr + 80004e0: 20000024 .word 0x20000024 + +080004e4 : + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_set(uint32_t gpioport, uint16_t gpios) +{ + GPIO_BSRR(gpioport) = gpios; + 80004e4: 6181 str r1, [r0, #24] +} + 80004e6: 4770 bx lr + +080004e8 : + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_clear(uint32_t gpioport, uint16_t gpios) +{ + GPIO_BSRR(gpioport) = (gpios << 16); + 80004e8: 0409 lsls r1, r1, #16 + 80004ea: 6181 str r1, [r0, #24] +} + 80004ec: 4770 bx lr + +080004ee : +@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id +@return Unsigned int16. The value held in the specified GPIO port. +*/ +uint16_t gpio_port_read(uint32_t gpioport) +{ + return (uint16_t)GPIO_IDR(gpioport); + 80004ee: 6900 ldr r0, [r0, #16] +} + 80004f0: 4008 ands r0, r1 + 80004f2: 4770 bx lr + +080004f4 : + uint32_t port = GPIO_ODR(gpioport); + 80004f4: 6943 ldr r3, [r0, #20] + GPIO_BSRR(gpioport) = ((port & gpios) << 16) | (~port & gpios); + 80004f6: ea01 0203 and.w r2, r1, r3 + 80004fa: ea21 0103 bic.w r1, r1, r3 + 80004fe: ea41 4102 orr.w r1, r1, r2, lsl #16 + 8000502: 6181 str r1, [r0, #24] +} + 8000504: 4770 bx lr + +08000506 : + If multiple pins are to be set, use bitwise OR '|' to separate + them. +*/ +void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, + uint16_t gpios) +{ + 8000506: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + + /* + * We want to set the config only for the pins mentioned in gpios, + * but keeping the others, so read out the actual config first. + */ + moder = GPIO_MODER(gpioport); + 800050a: 6805 ldr r5, [r0, #0] + pupd = GPIO_PUPDR(gpioport); + 800050c: 2600 movs r6, #0 + 800050e: 68c4 ldr r4, [r0, #12] + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) { + continue; + } + + moder &= ~GPIO_MODE_MASK(i); + 8000510: f04f 0e03 mov.w lr, #3 + if (!((1 << i) & gpios)) { + 8000514: fa43 f706 asr.w r7, r3, r6 + 8000518: 07ff lsls r7, r7, #31 + 800051a: d50d bpl.n 8000538 + moder &= ~GPIO_MODE_MASK(i); + 800051c: 0077 lsls r7, r6, #1 + 800051e: fa0e fc07 lsl.w ip, lr, r7 + moder |= GPIO_MODE(i, mode); + 8000522: fa01 f807 lsl.w r8, r1, r7 + pupd &= ~GPIO_PUPD_MASK(i); + pupd |= GPIO_PUPD(i, pull_up_down); + 8000526: fa02 f707 lsl.w r7, r2, r7 + moder &= ~GPIO_MODE_MASK(i); + 800052a: ea25 050c bic.w r5, r5, ip + pupd &= ~GPIO_PUPD_MASK(i); + 800052e: ea24 040c bic.w r4, r4, ip + moder |= GPIO_MODE(i, mode); + 8000532: ea48 0505 orr.w r5, r8, r5 + pupd |= GPIO_PUPD(i, pull_up_down); + 8000536: 433c orrs r4, r7 + for (i = 0; i < 16; i++) { + 8000538: 3601 adds r6, #1 + 800053a: 2e10 cmp r6, #16 + 800053c: d1ea bne.n 8000514 + } + + /* Set mode and pull up/down control registers. */ + GPIO_MODER(gpioport) = moder; + 800053e: 6005 str r5, [r0, #0] + GPIO_PUPDR(gpioport) = pupd; + 8000540: 60c4 str r4, [r0, #12] +} + 8000542: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + +08000546 : + uint16_t gpios) +{ + uint16_t i; + uint32_t ospeedr; + + if (otype == 0x1) { + 8000546: 2901 cmp r1, #1 + GPIO_OTYPER(gpioport) |= gpios; + 8000548: 6841 ldr r1, [r0, #4] + 800054a: bf0c ite eq + 800054c: 4319 orreq r1, r3 + } else { + GPIO_OTYPER(gpioport) &= ~gpios; + 800054e: 4399 bicne r1, r3 +{ + 8000550: b5f0 push {r4, r5, r6, r7, lr} + GPIO_OTYPER(gpioport) &= ~gpios; + 8000552: 6041 str r1, [r0, #4] + } + + ospeedr = GPIO_OSPEEDR(gpioport); + 8000554: 2400 movs r4, #0 + 8000556: 6881 ldr r1, [r0, #8] + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) { + continue; + } + ospeedr &= ~GPIO_OSPEED_MASK(i); + 8000558: 2603 movs r6, #3 + if (!((1 << i) & gpios)) { + 800055a: fa43 f504 asr.w r5, r3, r4 + 800055e: 07ed lsls r5, r5, #31 + 8000560: d507 bpl.n 8000572 + ospeedr &= ~GPIO_OSPEED_MASK(i); + 8000562: 0065 lsls r5, r4, #1 + 8000564: fa06 f705 lsl.w r7, r6, r5 + ospeedr |= GPIO_OSPEED(i, speed); + 8000568: fa02 f505 lsl.w r5, r2, r5 + ospeedr &= ~GPIO_OSPEED_MASK(i); + 800056c: ea21 0107 bic.w r1, r1, r7 + ospeedr |= GPIO_OSPEED(i, speed); + 8000570: 4329 orrs r1, r5 + for (i = 0; i < 16; i++) { + 8000572: 3401 adds r4, #1 + 8000574: 2c10 cmp r4, #16 + 8000576: d1f0 bne.n 800055a + } + + GPIO_OSPEEDR(gpioport) = ospeedr; + 8000578: 6081 str r1, [r0, #8] +} + 800057a: bdf0 pop {r4, r5, r6, r7, pc} + +0800057c : + .per.pclk2_mhz = RCC_HSI_BASE_FREQUENCY / HZ_PER_MHZ, + .per.pclk3_mhz = RCC_HSI_BASE_FREQUENCY / HZ_PER_MHZ, + .per.pclk4_mhz = RCC_HSI_BASE_FREQUENCY / HZ_PER_MHZ +}; + +static void rcc_configure_pll(uint32_t clkin, const struct pll_config *config, int pll_num) { + 800057c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + /* Only concern ourselves with the PLL if the input clock is enabled. */ + if (config->divm == 0 || pll_num < 1 || pll_num > 3) { + 8000580: f891 c000 ldrb.w ip, [r1] + 8000584: f1bc 0f00 cmp.w ip, #0 + 8000588: f000 80a5 beq.w 80006d6 + return; + } + + struct pll_clocks *pll_tree_ptr; + if (pll_num == 1) { + 800058c: 2a01 cmp r2, #1 + 800058e: d026 beq.n 80005de + pll_tree_ptr = &rcc_clock_tree.pll1; + } else if (pll_num == 2) { + pll_tree_ptr = &rcc_clock_tree.pll2; + 8000590: 4b57 ldr r3, [pc, #348] @ (80006f0 ) + 8000592: 1f9e subs r6, r3, #6 + 8000594: 2a02 cmp r2, #2 + 8000596: bf18 it ne + 8000598: 461e movne r6, r3 + } else { + pll_tree_ptr = &rcc_clock_tree.pll3; + } + + /* Let's write all of the dividers as specified. */ + RCC_PLLDIVR(pll_num) = 0; + 800059a: 3a01 subs r2, #1 + 800059c: 4d55 ldr r5, [pc, #340] @ (80006f4 ) + 800059e: 2300 movs r3, #0 + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVN(config->divn); + 80005a0: f8b1 8002 ldrh.w r8, [r1, #2] + RCC_PLLDIVR(pll_num) = 0; + 80005a4: f845 3032 str.w r3, [r5, r2, lsl #3] + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVN(config->divn); + 80005a8: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff + 80005ac: f855 4032 ldr.w r4, [r5, r2, lsl #3] + 80005b0: 4323 orrs r3, r4 + + /* Setup the PLL config values for this PLL. */ + uint8_t vco_addshift = 4 * (pll_num - 1); /* Values spaced by 4 for PLL 1/2/3 */ + 80005b2: b2d4 uxtb r4, r2 + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVN(config->divn); + 80005b4: f845 3032 str.w r3, [r5, r2, lsl #3] + uint8_t vco_addshift = 4 * (pll_num - 1); /* Values spaced by 4 for PLL 1/2/3 */ + 80005b8: 00a7 lsls r7, r4, #2 + + /* Set the PLL input frequency range. */ + uint32_t pll_clk_mhz = (clkin / config->divm) / HZ_PER_MHZ; + 80005ba: fbb0 f3fc udiv r3, r0, ip + 80005be: 484e ldr r0, [pc, #312] @ (80006f8 ) + uint8_t vco_addshift = 4 * (pll_num - 1); /* Values spaced by 4 for PLL 1/2/3 */ + 80005c0: b2ff uxtb r7, r7 + uint32_t pll_clk_mhz = (clkin / config->divm) / HZ_PER_MHZ; + 80005c2: fbb3 fcf0 udiv ip, r3, r0 + if (pll_clk_mhz > 2 && pll_clk_mhz <= 4) { + 80005c6: f1ac 0003 sub.w r0, ip, #3 + 80005ca: 2801 cmp r0, #1 + 80005cc: 484b ldr r0, [pc, #300] @ (80006fc ) + 80005ce: d808 bhi.n 80005e2 + RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_2_4MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; + 80005d0: 2304 movs r3, #4 + 80005d2: f8d0 e42c ldr.w lr, [r0, #1068] @ 0x42c + 80005d6: 40bb lsls r3, r7 + } else if (pll_clk_mhz > 4 && pll_clk_mhz <= 8) { + RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_4_8MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; + } else if (pll_clk_mhz > 8) { + RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_8_16MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; + 80005d8: ea4e 0303 orr.w r3, lr, r3 + 80005dc: e00d b.n 80005fa + pll_tree_ptr = &rcc_clock_tree.pll1; + 80005de: 4e48 ldr r6, [pc, #288] @ (8000700 ) + 80005e0: e7db b.n 800059a + } else if (pll_clk_mhz > 4 && pll_clk_mhz <= 8) { + 80005e2: f1ac 0e05 sub.w lr, ip, #5 + 80005e6: f1be 0f03 cmp.w lr, #3 + 80005ea: d876 bhi.n 80006da + RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_4_8MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; + 80005ec: 2308 movs r3, #8 + 80005ee: f8d0 942c ldr.w r9, [r0, #1068] @ 0x42c + 80005f2: fa03 fe07 lsl.w lr, r3, r7 + 80005f6: ea4e 0309 orr.w r3, lr, r9 + RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_8_16MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; + 80005fa: f8c0 342c str.w r3, [r0, #1068] @ 0x42c + } + + /* Set the VCO output frequency range. */ + uint32_t pll_vco_clk_mhz = (pll_clk_mhz * config->divn); + 80005fe: fb0c f308 mul.w r3, ip, r8 + if (pll_vco_clk_mhz <= 420) { + 8000602: f5b3 7fd2 cmp.w r3, #420 @ 0x1a4 + 8000606: d809 bhi.n 800061c + RCC_PLLCFGR |= (RCC_PLLCFGR_PLL1VCO_MED << vco_addshift); + 8000608: f8df c0f0 ldr.w ip, [pc, #240] @ 80006fc + 800060c: 2002 movs r0, #2 + 800060e: f8dc e42c ldr.w lr, [ip, #1068] @ 0x42c + 8000612: 40b8 lsls r0, r7 + 8000614: ea40 000e orr.w r0, r0, lr + 8000618: f8cc 042c str.w r0, [ip, #1068] @ 0x42c + } + + /* Setup the enable bits for the PLL outputs. */ + uint8_t diven_addshift = 3 * (pll_num - 1); /* Values spaced by 3 for PLL1/2/3 */ + 800061c: 0067 lsls r7, r4, #1 + if (config->divp > 0) { + 800061e: 7908 ldrb r0, [r1, #4] + uint8_t diven_addshift = 3 * (pll_num - 1); /* Values spaced by 3 for PLL1/2/3 */ + 8000620: eb04 0444 add.w r4, r4, r4, lsl #1 + 8000624: b2e4 uxtb r4, r4 + if (config->divp > 0) { + 8000626: b1b0 cbz r0, 8000656 + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVP(config->divp); + 8000628: f855 c032 ldr.w ip, [r5, r2, lsl #3] + 800062c: f100 3eff add.w lr, r0, #4294967295 @ 0xffffffff + 8000630: ea4c 2c4e orr.w ip, ip, lr, lsl #9 + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVP1EN << diven_addshift); + 8000634: f8df e0c4 ldr.w lr, [pc, #196] @ 80006fc + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVP(config->divp); + 8000638: f845 c032 str.w ip, [r5, r2, lsl #3] + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVP1EN << diven_addshift); + 800063c: f44f 3c80 mov.w ip, #65536 @ 0x10000 + 8000640: f8de 842c ldr.w r8, [lr, #1068] @ 0x42c + 8000644: fa0c fc04 lsl.w ip, ip, r4 + pll_tree_ptr->p_mhz = pll_vco_clk_mhz / config->divp; + 8000648: fbb3 f0f0 udiv r0, r3, r0 + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVP1EN << diven_addshift); + 800064c: ea4c 0c08 orr.w ip, ip, r8 + 8000650: f8ce c42c str.w ip, [lr, #1068] @ 0x42c + pll_tree_ptr->p_mhz = pll_vco_clk_mhz / config->divp; + 8000654: 8030 strh r0, [r6, #0] + } + if (config->divq > 0) { + 8000656: 7948 ldrb r0, [r1, #5] + 8000658: b1b0 cbz r0, 8000688 + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVQ(config->divq); + 800065a: f855 c032 ldr.w ip, [r5, r2, lsl #3] + 800065e: f100 3eff add.w lr, r0, #4294967295 @ 0xffffffff + 8000662: ea4c 4c0e orr.w ip, ip, lr, lsl #16 + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVQ1EN << diven_addshift); + 8000666: f8df e094 ldr.w lr, [pc, #148] @ 80006fc + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVQ(config->divq); + 800066a: f845 c032 str.w ip, [r5, r2, lsl #3] + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVQ1EN << diven_addshift); + 800066e: f44f 3c00 mov.w ip, #131072 @ 0x20000 + 8000672: f8de 842c ldr.w r8, [lr, #1068] @ 0x42c + 8000676: fa0c fc04 lsl.w ip, ip, r4 + pll_tree_ptr->q_mhz = pll_vco_clk_mhz / config->divq; + 800067a: fbb3 f0f0 udiv r0, r3, r0 + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVQ1EN << diven_addshift); + 800067e: ea4c 0c08 orr.w ip, ip, r8 + 8000682: f8ce c42c str.w ip, [lr, #1068] @ 0x42c + pll_tree_ptr->q_mhz = pll_vco_clk_mhz / config->divq; + 8000686: 8070 strh r0, [r6, #2] + } + if (config->divr > 0) { + 8000688: 7989 ldrb r1, [r1, #6] + 800068a: b199 cbz r1, 80006b4 + RCC_PLLDIVR(pll_num) |= RCC_PLLNDIVR_DIVR(config->divr); + 800068c: f855 0032 ldr.w r0, [r5, r2, lsl #3] + 8000690: f101 3cff add.w ip, r1, #4294967295 @ 0xffffffff + 8000694: ea40 600c orr.w r0, r0, ip, lsl #24 + 8000698: f845 0032 str.w r0, [r5, r2, lsl #3] + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVR1EN << diven_addshift); + 800069c: f44f 2280 mov.w r2, #262144 @ 0x40000 + 80006a0: 4816 ldr r0, [pc, #88] @ (80006fc ) + 80006a2: 40a2 lsls r2, r4 + 80006a4: f8d0 542c ldr.w r5, [r0, #1068] @ 0x42c + pll_tree_ptr->r_mhz = pll_vco_clk_mhz / config->divr; + 80006a8: fbb3 f3f1 udiv r3, r3, r1 + RCC_PLLCFGR |= (RCC_PLLCFGR_DIVR1EN << diven_addshift); + 80006ac: 432a orrs r2, r5 + 80006ae: f8c0 242c str.w r2, [r0, #1068] @ 0x42c + pll_tree_ptr->r_mhz = pll_vco_clk_mhz / config->divr; + 80006b2: 80b3 strh r3, [r6, #4] + } + + /* Attempt to enable and lock PLL. */ + uint8_t cr_addshift = 2 * (pll_num - 1); + RCC_CR |= RCC_CR_PLL1ON << cr_addshift; + 80006b4: 4a11 ldr r2, [pc, #68] @ (80006fc ) + 80006b6: b2ff uxtb r7, r7 + 80006b8: f04f 7380 mov.w r3, #16777216 @ 0x1000000 + 80006bc: f8d2 1400 ldr.w r1, [r2, #1024] @ 0x400 + 80006c0: 40bb lsls r3, r7 + 80006c2: 430b orrs r3, r1 + 80006c4: f8c2 3400 str.w r3, [r2, #1024] @ 0x400 + while (!(RCC_CR & (RCC_CR_PLL1RDY << cr_addshift))); + 80006c8: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 80006cc: 40bb lsls r3, r7 + 80006ce: f8d2 1400 ldr.w r1, [r2, #1024] @ 0x400 + 80006d2: 4219 tst r1, r3 + 80006d4: d0fb beq.n 80006ce +} + 80006d6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + } else if (pll_clk_mhz > 8) { + 80006da: f8df e028 ldr.w lr, [pc, #40] @ 8000704 + 80006de: 4573 cmp r3, lr + 80006e0: d98d bls.n 80005fe + RCC_PLLCFGR |= (RCC_PLLCFGR_PLLRGE_8_16MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT) << vco_addshift; + 80006e2: f04f 0e0c mov.w lr, #12 + 80006e6: f8d0 342c ldr.w r3, [r0, #1068] @ 0x42c + 80006ea: fa0e fe07 lsl.w lr, lr, r7 + 80006ee: e773 b.n 80005d8 + 80006f0: 2000001a .word 0x2000001a + 80006f4: 58024430 .word 0x58024430 + 80006f8: 000f4240 .word 0x000f4240 + 80006fc: 58024000 .word 0x58024000 + 8000700: 2000000e .word 0x2000000e + 8000704: 0089543f .word 0x0089543f + +08000708 : + /* Update our clock values in our tree based on the config values. */ + rcc_clock_tree.per.pclk4_mhz = + rcc_prediv_3bit_log_div(rcc_clock_tree.hclk_mhz, config->ppre4); +} + +void rcc_clock_setup_pll(const struct rcc_pll_config *config) { + 8000708: b5f8 push {r3, r4, r5, r6, r7, lr} + /* First, set system clock to utilize HSI, then disable all but HSI. */ + RCC_CR |= RCC_CR_HSION; + 800070a: 4b81 ldr r3, [pc, #516] @ (8000910 ) +void rcc_clock_setup_pll(const struct rcc_pll_config *config) { + 800070c: 4604 mov r4, r0 + RCC_CR |= RCC_CR_HSION; + 800070e: f8d3 2400 ldr.w r2, [r3, #1024] @ 0x400 + 8000712: f042 0201 orr.w r2, r2, #1 + 8000716: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 + RCC_CFGR &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT); + 800071a: f8d3 2410 ldr.w r2, [r3, #1040] @ 0x410 + 800071e: f022 0207 bic.w r2, r2, #7 + 8000722: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 + while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI); + 8000726: f8d3 2410 ldr.w r2, [r3, #1040] @ 0x410 + 800072a: f012 0f38 tst.w r2, #56 @ 0x38 + 800072e: d1fa bne.n 8000726 + RCC_CR = RCC_CR_HSION; + 8000730: 2201 movs r2, #1 + 8000732: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 + + /* Now that we're safely running on HSI, let's setup the power system for scaling. */ + pwr_set_mode(config->power_mode, config->smps_level); + 8000736: f894 1029 ldrb.w r1, [r4, #41] @ 0x29 + 800073a: f894 0028 ldrb.w r0, [r4, #40] @ 0x28 + 800073e: f000 fa2f bl 8000ba0 + pwr_set_vos_scale(config->voltage_scale); + 8000742: f894 0027 ldrb.w r0, [r4, #39] @ 0x27 + 8000746: f000 fa57 bl 8000bf8 + + /* Set flash waitstates. Enable flash prefetch if we have at least 1WS */ + flash_set_ws(config->flash_waitstates); + 800074a: f894 0026 ldrb.w r0, [r4, #38] @ 0x26 + 800074e: f000 f9d3 bl 8000af8 + if (config->flash_waitstates > FLASH_ACR_LATENCY_0WS) { + 8000752: f894 3026 ldrb.w r3, [r4, #38] @ 0x26 + 8000756: 2b00 cmp r3, #0 + 8000758: f000 80c5 beq.w 80008e6 + flash_prefetch_enable(); + 800075c: f000 f9bc bl 8000ad8 + } else { + flash_prefetch_disable(); + } + + /* User has specified an external oscillator, make sure we turn it on. */ + if (config->hse_frequency > 0) { + 8000760: 6863 ldr r3, [r4, #4] + 8000762: b18b cbz r3, 8000788 + RCC_CR |= RCC_CR_HSEON; + 8000764: 4b6a ldr r3, [pc, #424] @ (8000910 ) + 8000766: f8d3 2400 ldr.w r2, [r3, #1024] @ 0x400 + 800076a: f442 3280 orr.w r2, r2, #65536 @ 0x10000 + 800076e: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 + while (!(RCC_CR & RCC_CR_HSERDY)); + 8000772: f8d3 2400 ldr.w r2, [r3, #1024] @ 0x400 + 8000776: 0392 lsls r2, r2, #14 + 8000778: d5fb bpl.n 8000772 + rcc_clock_tree.hse_khz = config->hse_frequency / HZ_PER_KHZ; + 800077a: 6863 ldr r3, [r4, #4] + 800077c: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8000780: fbb3 f3f2 udiv r3, r3, r2 + 8000784: 4a63 ldr r2, [pc, #396] @ (8000914 ) + 8000786: 8413 strh r3, [r2, #32] + RCC_PLLCKSELR_DIVM2(config->pll2.divm) | + 8000788: 7c23 ldrb r3, [r4, #16] + RCC_PLLCKSELR = RCC_PLLCKSELR_DIVM1(config->pll1.divm) | + 800078a: 7a22 ldrb r2, [r4, #8] + RCC_PLLCKSELR_DIVM2(config->pll2.divm) | + 800078c: 031b lsls r3, r3, #12 + config->pll_source; + 800078e: 7861 ldrb r1, [r4, #1] + RCC_PLLCKSELR = RCC_PLLCKSELR_DIVM1(config->pll1.divm) | + 8000790: ea43 1302 orr.w r3, r3, r2, lsl #4 + RCC_PLLCKSELR_DIVM3(config->pll3.divm) | + 8000794: 7e22 ldrb r2, [r4, #24] + 8000796: 430b orrs r3, r1 + 8000798: ea43 5302 orr.w r3, r3, r2, lsl #20 + RCC_PLLCKSELR = RCC_PLLCKSELR_DIVM1(config->pll1.divm) | + 800079c: 4a5c ldr r2, [pc, #368] @ (8000910 ) + 800079e: f8c2 3428 str.w r3, [r2, #1064] @ 0x428 + ? RCC_HSI_BASE_FREQUENCY : config->hse_frequency; + 80007a2: 2900 cmp r1, #0 + 80007a4: f000 80a2 beq.w 80008ec + 80007a8: 6865 ldr r5, [r4, #4] + RCC_PLLCFGR = 0; + 80007aa: 2300 movs r3, #0 + rcc_configure_pll(clkin, &config->pll1, 1); + 80007ac: f104 0108 add.w r1, r4, #8 + 80007b0: 4628 mov r0, r5 + RCC_PLLCFGR = 0; + 80007b2: f8c2 342c str.w r3, [r2, #1068] @ 0x42c + rcc_configure_pll(clkin, &config->pll1, 1); + 80007b6: 2201 movs r2, #1 + 80007b8: f7ff fee0 bl 800057c + rcc_configure_pll(clkin, &config->pll2, 2); + 80007bc: 2202 movs r2, #2 + 80007be: f104 0110 add.w r1, r4, #16 + 80007c2: 4628 mov r0, r5 + 80007c4: f7ff feda bl 800057c + rcc_configure_pll(clkin, &config->pll3, 3); + 80007c8: 4628 mov r0, r5 + 80007ca: 2203 movs r2, #3 + 80007cc: f104 0118 add.w r1, r4, #24 + 80007d0: f7ff fed4 bl 800057c + + /* Set, enable and lock all of the pll from the config. */ + rcc_set_and_enable_plls(config); + + /* Populate our base sysclk settings for use with domain clocks. */ + if (config->sysclock_source == RCC_PLL) { + 80007d4: 7823 ldrb r3, [r4, #0] + 80007d6: 484f ldr r0, [pc, #316] @ (8000914 ) + 80007d8: 2b00 cmp r3, #0 + 80007da: f040 8089 bne.w 80008f0 + rcc_clock_tree.sysclk_mhz = rcc_clock_tree.pll1.p_mhz; + 80007de: 89c3 ldrh r3, [r0, #14] + 80007e0: f894 5024 ldrb.w r5, [r4, #36] @ 0x24 + RCC_D1CFGR = 0; + 80007e4: 2600 movs r6, #0 + 80007e6: 4f4a ldr r7, [pc, #296] @ (8000910 ) + 80007e8: f894 1020 ldrb.w r1, [r4, #32] + 80007ec: f894 2021 ldrb.w r2, [r4, #33] @ 0x21 + rcc_clock_tree.sysclk_mhz = rcc_clock_tree.pll1.p_mhz; + 80007f0: 8003 strh r3, [r0, #0] + if (div_val < 0x8) { + 80007f2: 2907 cmp r1, #7 + RCC_D1CFGR = 0; + 80007f4: f8c7 6418 str.w r6, [r7, #1048] @ 0x418 + RCC_D1CFGR_D1HPRE(config->hpre) | RCC_D1CFGR_D1PPRE(config->ppre3); + 80007f8: ea4f 1605 mov.w r6, r5, lsl #4 + RCC_D1CFGR |= RCC_D1CFGR_D1CPRE(config->core_pre) | + 80007fc: f8d7 c418 ldr.w ip, [r7, #1048] @ 0x418 + RCC_D1CFGR_D1HPRE(config->hpre) | RCC_D1CFGR_D1PPRE(config->ppre3); + 8000800: ea46 2601 orr.w r6, r6, r1, lsl #8 + 8000804: ea46 0602 orr.w r6, r6, r2 + RCC_D1CFGR |= RCC_D1CFGR_D1CPRE(config->core_pre) | + 8000808: ea46 060c orr.w r6, r6, ip + 800080c: f8c7 6418 str.w r6, [r7, #1048] @ 0x418 + if (div_val < 0x8) { + 8000810: d906 bls.n 8000820 + } else if (div_val <= RCC_D1CFGR_D1CPRE_DIV16) { + 8000812: 290b cmp r1, #11 + return clk_mhz >> (div_val - 7); + 8000814: bf94 ite ls + 8000816: 3907 subls r1, #7 + return clk_mhz >> (div_val - 6); + 8000818: 3906 subhi r1, #6 + 800081a: fa43 f101 asr.w r1, r3, r1 + 800081e: b28b uxth r3, r1 + if (div_val < 0x8) { + 8000820: 2a07 cmp r2, #7 + rcc_clock_tree.cpu_mhz = + 8000822: 8043 strh r3, [r0, #2] + if (div_val < 0x8) { + 8000824: d909 bls.n 800083a + } else if (div_val <= RCC_D1CFGR_D1CPRE_DIV16) { + 8000826: 2a0b cmp r2, #11 + return clk_mhz >> (div_val - 7); + 8000828: bf95 itete ls + 800082a: 3a07 subls r2, #7 + return clk_mhz >> (div_val - 6); + 800082c: 1f91 subhi r1, r2, #6 + return clk_mhz >> (div_val - 7); + 800082e: fa43 f202 asrls.w r2, r3, r2 + return clk_mhz >> (div_val - 6); + 8000832: 410b asrhi r3, r1 + return clk_mhz >> (div_val - 7); + 8000834: bf94 ite ls + 8000836: b293 uxthls r3, r2 + return clk_mhz >> (div_val - 6); + 8000838: b29b uxthhi r3, r3 + if (div_val < 0x4) { + 800083a: 2d03 cmp r5, #3 + 800083c: f894 1023 ldrb.w r1, [r4, #35] @ 0x23 + RCC_D2CFGR = 0; + 8000840: 4e33 ldr r6, [pc, #204] @ (8000910 ) + return clk_mhz >> (div_val - 3); + 8000842: bf8c ite hi + 8000844: 1eea subhi r2, r5, #3 + return clk_mhz; + 8000846: 461a movls r2, r3 + RCC_D2CFGR = 0; + 8000848: f04f 0500 mov.w r5, #0 + rcc_clock_tree.hclk_mhz = + 800084c: 8083 strh r3, [r0, #4] + return clk_mhz >> (div_val - 3); + 800084e: bf84 itt hi + 8000850: fa43 f202 asrhi.w r2, r3, r2 + 8000854: b292 uxthhi r2, r2 + if (div_val < 0x4) { + 8000856: 2903 cmp r1, #3 + rcc_clock_tree.per.pclk3_mhz = + 8000858: 8142 strh r2, [r0, #10] + RCC_D2CFGR = 0; + 800085a: f894 2022 ldrb.w r2, [r4, #34] @ 0x22 + 800085e: f8c6 541c str.w r5, [r6, #1052] @ 0x41c + RCC_D2CFGR_D2PPRE2(config->ppre2); + 8000862: ea4f 2501 mov.w r5, r1, lsl #8 + return clk_mhz >> (div_val - 3); + 8000866: bf8c ite hi + 8000868: 3903 subhi r1, #3 + return clk_mhz; + 800086a: 4619 movls r1, r3 + RCC_D2CFGR |= RCC_D2CFGR_D2PPRE1(config->ppre1) | + 800086c: ea45 1502 orr.w r5, r5, r2, lsl #4 + 8000870: f8d6 741c ldr.w r7, [r6, #1052] @ 0x41c + return clk_mhz >> (div_val - 3); + 8000874: bf88 it hi + 8000876: fa43 f101 asrhi.w r1, r3, r1 + RCC_D2CFGR |= RCC_D2CFGR_D2PPRE1(config->ppre1) | + 800087a: ea45 0507 orr.w r5, r5, r7 + return clk_mhz >> (div_val - 3); + 800087e: bf88 it hi + 8000880: b289 uxthhi r1, r1 + if (div_val < 0x4) { + 8000882: 2a03 cmp r2, #3 + RCC_D2CFGR |= RCC_D2CFGR_D2PPRE1(config->ppre1) | + 8000884: f8c6 541c str.w r5, [r6, #1052] @ 0x41c + return clk_mhz >> (div_val - 3); + 8000888: bf8c ite hi + 800088a: 3a03 subhi r2, #3 + return clk_mhz; + 800088c: 461a movls r2, r3 + rcc_clock_tree.per.pclk2_mhz = + 800088e: 8101 strh r1, [r0, #8] + return clk_mhz >> (div_val - 3); + 8000890: bf88 it hi + 8000892: fa43 f202 asrhi.w r2, r3, r2 + 8000896: f894 1025 ldrb.w r1, [r4, #37] @ 0x25 + 800089a: bf88 it hi + 800089c: b292 uxthhi r2, r2 + if (div_val < 0x4) { + 800089e: 2903 cmp r1, #3 + rcc_clock_tree.per.pclk1_mhz = + 80008a0: 80c2 strh r2, [r0, #6] + RCC_D3CFGR &= 0; + 80008a2: 4a1b ldr r2, [pc, #108] @ (8000910 ) + 80008a4: f8d2 4420 ldr.w r4, [r2, #1056] @ 0x420 + 80008a8: f04f 0400 mov.w r4, #0 + 80008ac: f8c2 4420 str.w r4, [r2, #1056] @ 0x420 + RCC_D3CFGR |= RCC_D3CFGR_D3PPRE(config->ppre4); + 80008b0: f8d2 4420 ldr.w r4, [r2, #1056] @ 0x420 + 80008b4: ea44 1401 orr.w r4, r4, r1, lsl #4 + return clk_mhz >> (div_val - 3); + 80008b8: bf84 itt hi + 80008ba: 3903 subhi r1, #3 + 80008bc: fa43 f101 asrhi.w r1, r3, r1 + RCC_D3CFGR |= RCC_D3CFGR_D3PPRE(config->ppre4); + 80008c0: f8c2 4420 str.w r4, [r2, #1056] @ 0x420 + return clk_mhz >> (div_val - 3); + 80008c4: bf88 it hi + 80008c6: b28b uxthhi r3, r1 + rcc_clock_tree.per.pclk4_mhz = + 80008c8: 8183 strh r3, [r0, #12] + rcc_clock_setup_domain3(config); + + /* TODO: Configure custom kernel mappings. */ + + /* Domains dividers are all configured, now we can switchover to PLL. */ + RCC_CFGR |= RCC_CFGR_SW_PLL1; + 80008ca: f8d2 3410 ldr.w r3, [r2, #1040] @ 0x410 + 80008ce: f043 0303 orr.w r3, r3, #3 + 80008d2: f8c2 3410 str.w r3, [r2, #1040] @ 0x410 + uint32_t cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK); + 80008d6: f8d2 3410 ldr.w r3, [r2, #1040] @ 0x410 + while(cfgr_sws != RCC_CFGR_SWS_PLL1) { + cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK); + 80008da: 4a0d ldr r2, [pc, #52] @ (8000910 ) + uint32_t cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK); + 80008dc: f3c3 03c2 ubfx r3, r3, #3, #3 + while(cfgr_sws != RCC_CFGR_SWS_PLL1) { + 80008e0: 2b03 cmp r3, #3 + 80008e2: d10f bne.n 8000904 + } +} + 80008e4: bdf8 pop {r3, r4, r5, r6, r7, pc} + flash_prefetch_disable(); + 80008e6: f000 f8ff bl 8000ae8 + 80008ea: e739 b.n 8000760 + ? RCC_HSI_BASE_FREQUENCY : config->hse_frequency; + 80008ec: 4d0a ldr r5, [pc, #40] @ (8000918 ) + 80008ee: e75c b.n 80007aa + } else if (config->sysclock_source == RCC_HSE) { + 80008f0: 2b01 cmp r3, #1 + rcc_clock_tree.sysclk_mhz = config->hse_frequency / HZ_PER_MHZ; + 80008f2: bf09 itett eq + 80008f4: 6863 ldreq r3, [r4, #4] + 80008f6: 2340 movne r3, #64 @ 0x40 + 80008f8: 4a08 ldreq r2, [pc, #32] @ (800091c ) + 80008fa: fbb3 f3f2 udiveq r3, r3, r2 + 80008fe: bf08 it eq + 8000900: b29b uxtheq r3, r3 + 8000902: e76d b.n 80007e0 + cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK); + 8000904: f8d2 3410 ldr.w r3, [r2, #1040] @ 0x410 + 8000908: f3c3 03c2 ubfx r3, r3, #3, #3 + 800090c: e7e8 b.n 80008e0 + 800090e: bf00 nop + 8000910: 58024000 .word 0x58024000 + 8000914: 20000000 .word 0x20000000 + 8000918: 03d09000 .word 0x03d09000 + 800091c: 000f4240 .word 0x000f4240 + +08000920 : + +uint32_t rcc_get_bus_clk_freq(enum rcc_clock_source source) { + 8000920: b508 push {r3, lr} + uint32_t clksel; + switch (source) { + 8000922: 2809 cmp r0, #9 + 8000924: d82c bhi.n 8000980 + 8000926: e8df f000 tbb [pc, r0] + 800092a: 050a .short 0x050a + 800092c: 0d0d0a1c .word 0x0d0d0a1c + 8000930: 19161310 .word 0x19161310 + case RCC_SYSCLK: + return rcc_clock_tree.sysclk_mhz * HZ_PER_MHZ; + 8000934: 4b15 ldr r3, [pc, #84] @ (800098c ) + 8000936: 8818 ldrh r0, [r3, #0] + case RCC_CPUCLK: + case RCC_SYSTICKCLK: + return rcc_clock_tree.cpu_mhz * HZ_PER_MHZ; + 8000938: 4b15 ldr r3, [pc, #84] @ (8000990 ) + case RCC_PERCLK: + clksel = (RCC_D1CCIPR >> RCC_D1CCIPR_CKPERSEL_SHIFT) & RCC_D1CCIPR_CKPERSEL_MASK; + if (clksel == RCC_D1CCIPR_CKPERSEL_HSI) { + return RCC_HSI_BASE_FREQUENCY; + } else if (clksel == RCC_D1CCIPR_CKPERSEL_HSE) { + return rcc_clock_tree.hse_khz * HZ_PER_KHZ; + 800093a: 4358 muls r0, r3 + } + default: + cm3_assert_not_reached(); + return 0U; + } +} + 800093c: bd08 pop {r3, pc} + return rcc_clock_tree.cpu_mhz * HZ_PER_MHZ; + 800093e: 4b13 ldr r3, [pc, #76] @ (800098c ) + 8000940: 8858 ldrh r0, [r3, #2] + 8000942: e7f9 b.n 8000938 + return rcc_clock_tree.hclk_mhz * HZ_PER_MHZ; + 8000944: 4b11 ldr r3, [pc, #68] @ (800098c ) + 8000946: 8898 ldrh r0, [r3, #4] + 8000948: e7f6 b.n 8000938 + return rcc_clock_tree.per.pclk1_mhz * HZ_PER_MHZ; + 800094a: 4b10 ldr r3, [pc, #64] @ (800098c ) + 800094c: 88d8 ldrh r0, [r3, #6] + 800094e: e7f3 b.n 8000938 + return rcc_clock_tree.per.pclk2_mhz * HZ_PER_MHZ; + 8000950: 4b0e ldr r3, [pc, #56] @ (800098c ) + 8000952: 8918 ldrh r0, [r3, #8] + 8000954: e7f0 b.n 8000938 + return rcc_clock_tree.per.pclk3_mhz * HZ_PER_MHZ; + 8000956: 4b0d ldr r3, [pc, #52] @ (800098c ) + 8000958: 8958 ldrh r0, [r3, #10] + 800095a: e7ed b.n 8000938 + return rcc_clock_tree.per.pclk4_mhz * HZ_PER_MHZ; + 800095c: 4b0b ldr r3, [pc, #44] @ (800098c ) + 800095e: 8998 ldrh r0, [r3, #12] + 8000960: e7ea b.n 8000938 + clksel = (RCC_D1CCIPR >> RCC_D1CCIPR_CKPERSEL_SHIFT) & RCC_D1CCIPR_CKPERSEL_MASK; + 8000962: 4b0c ldr r3, [pc, #48] @ (8000994 ) + 8000964: f8d3 344c ldr.w r3, [r3, #1100] @ 0x44c + if (clksel == RCC_D1CCIPR_CKPERSEL_HSI) { + 8000968: f013 5f40 tst.w r3, #805306368 @ 0x30000000 + clksel = (RCC_D1CCIPR >> RCC_D1CCIPR_CKPERSEL_SHIFT) & RCC_D1CCIPR_CKPERSEL_MASK; + 800096c: f3c3 7201 ubfx r2, r3, #28, #2 + if (clksel == RCC_D1CCIPR_CKPERSEL_HSI) { + 8000970: d008 beq.n 8000984 + } else if (clksel == RCC_D1CCIPR_CKPERSEL_HSE) { + 8000972: 2a02 cmp r2, #2 + 8000974: d108 bne.n 8000988 + return rcc_clock_tree.hse_khz * HZ_PER_KHZ; + 8000976: 4b05 ldr r3, [pc, #20] @ (800098c ) + 8000978: 8c18 ldrh r0, [r3, #32] + 800097a: f44f 737a mov.w r3, #1000 @ 0x3e8 + 800097e: e7dc b.n 800093a + cm3_assert_not_reached(); + 8000980: f000 f8a8 bl 8000ad4 + return RCC_HSI_BASE_FREQUENCY; + 8000984: 4804 ldr r0, [pc, #16] @ (8000998 ) + 8000986: e7d9 b.n 800093c + return 0U; + 8000988: 2000 movs r0, #0 + 800098a: e7d7 b.n 800093c + 800098c: 20000000 .word 0x20000000 + 8000990: 000f4240 .word 0x000f4240 + 8000994: 58024000 .word 0x58024000 + 8000998: 03d09000 .word 0x03d09000 + +0800099c : + * + * For available constants, see #rcc_periph_clken (RCC_UART1 for example) + */ +void rcc_periph_clock_enable(enum rcc_periph_clken clken) +{ + _RCC_REG(clken) |= _RCC_BIT(clken); + 800099c: 0943 lsrs r3, r0, #5 + 800099e: 2201 movs r2, #1 + 80009a0: f000 001f and.w r0, r0, #31 + 80009a4: f103 43b0 add.w r3, r3, #1476395008 @ 0x58000000 + 80009a8: 4082 lsls r2, r0 + 80009aa: f503 3311 add.w r3, r3, #148480 @ 0x24400 + 80009ae: 6819 ldr r1, [r3, #0] + 80009b0: 430a orrs r2, r1 + 80009b2: 601a str r2, [r3, #0] +} + 80009b4: 4770 bx lr + +080009b6 : + +} + +void blocking_handler(void) +{ + while (1); + 80009b6: e7fe b.n 80009b6 + +080009b8 : +} + +void null_handler(void) +{ + /* Do nothing. */ +} + 80009b8: 4770 bx lr + ... + +080009bc : +{ + 80009bc: b538 push {r3, r4, r5, lr} + for (src = &_data_loadaddr, dest = &_data; + 80009be: 4a1d ldr r2, [pc, #116] @ (8000a34 ) + 80009c0: 4b1d ldr r3, [pc, #116] @ (8000a38 ) + dest < &_edata; + 80009c2: 491e ldr r1, [pc, #120] @ (8000a3c ) + 80009c4: 428b cmp r3, r1 + 80009c6: d320 bcc.n 8000a0a + while (dest < &_ebss) { + 80009c8: 4a1d ldr r2, [pc, #116] @ (8000a40 ) + *dest++ = 0; + 80009ca: 2100 movs r1, #0 + while (dest < &_ebss) { + 80009cc: 4293 cmp r3, r2 + 80009ce: d321 bcc.n 8000a14 + SCB_CCR |= SCB_CCR_STKALIGN; + 80009d0: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 + for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) { + 80009d4: 4c1b ldr r4, [pc, #108] @ (8000a44 ) + 80009d6: 4d1c ldr r5, [pc, #112] @ (8000a48 ) + SCB_CCR |= SCB_CCR_STKALIGN; + 80009d8: f8d3 2d14 ldr.w r2, [r3, #3348] @ 0xd14 + 80009dc: f442 7200 orr.w r2, r2, #512 @ 0x200 + 80009e0: f8c3 2d14 str.w r2, [r3, #3348] @ 0xd14 +#include + +static void pre_main(void) +{ + /* Enable access to Floating-Point coprocessor. */ + SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); + 80009e4: f8d3 2d88 ldr.w r2, [r3, #3464] @ 0xd88 + 80009e8: f442 0270 orr.w r2, r2, #15728640 @ 0xf00000 + 80009ec: f8c3 2d88 str.w r2, [r3, #3464] @ 0xd88 + for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) { + 80009f0: 42ac cmp r4, r5 + 80009f2: d312 bcc.n 8000a1a + for (fp = &__init_array_start; fp < &__init_array_end; fp++) { + 80009f4: 4c15 ldr r4, [pc, #84] @ (8000a4c ) + 80009f6: 4d16 ldr r5, [pc, #88] @ (8000a50 ) + 80009f8: 42ac cmp r4, r5 + 80009fa: d312 bcc.n 8000a22 + for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) { + 80009fc: 4c15 ldr r4, [pc, #84] @ (8000a54 ) + (void)main(); + 80009fe: f7ff fc7b bl 80002f8
+ for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) { + 8000a02: 4d15 ldr r5, [pc, #84] @ (8000a58 ) + 8000a04: 42ac cmp r4, r5 + 8000a06: d310 bcc.n 8000a2a +} + 8000a08: bd38 pop {r3, r4, r5, pc} + *dest = *src; + 8000a0a: f852 0b04 ldr.w r0, [r2], #4 + 8000a0e: f843 0b04 str.w r0, [r3], #4 + src++, dest++) { + 8000a12: e7d7 b.n 80009c4 + *dest++ = 0; + 8000a14: f843 1b04 str.w r1, [r3], #4 + 8000a18: e7d8 b.n 80009cc + (*fp)(); + 8000a1a: f854 3b04 ldr.w r3, [r4], #4 + 8000a1e: 4798 blx r3 + for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) { + 8000a20: e7e6 b.n 80009f0 + (*fp)(); + 8000a22: f854 3b04 ldr.w r3, [r4], #4 + 8000a26: 4798 blx r3 + for (fp = &__init_array_start; fp < &__init_array_end; fp++) { + 8000a28: e7e6 b.n 80009f8 + (*fp)(); + 8000a2a: f854 3b04 ldr.w r3, [r4], #4 + 8000a2e: 4798 blx r3 + for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) { + 8000a30: e7e8 b.n 8000a04 + 8000a32: bf00 nop + 8000a34: 08000d38 .word 0x08000d38 + 8000a38: 20000000 .word 0x20000000 + 8000a3c: 20000024 .word 0x20000024 + 8000a40: 20000028 .word 0x20000028 + 8000a44: 08000d38 .word 0x08000d38 + 8000a48: 08000d38 .word 0x08000d38 + 8000a4c: 08000d38 .word 0x08000d38 + 8000a50: 08000d38 .word 0x08000d38 + 8000a54: 08000d38 .word 0x08000d38 + 8000a58: 08000d38 .word 0x08000d38 + +08000a5c : + * + * @param[in] value uint32_t. 24 bit reload value. + */ +void systick_set_reload(uint32_t value) +{ + STK_RVR = (value & STK_RVR_RELOAD); + 8000a5c: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 + 8000a60: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 + 8000a64: 6158 str r0, [r3, #20] +} + 8000a66: 4770 bx lr + +08000a68 : + * @param[in] clocksource uint8_t. Clock source from @ref systick_clksource. + */ + +void systick_set_clocksource(uint8_t clocksource) +{ + STK_CSR = (STK_CSR & ~STK_CSR_CLKSOURCE) | + 8000a68: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 + (clocksource & STK_CSR_CLKSOURCE); + 8000a6c: f000 0004 and.w r0, r0, #4 + STK_CSR = (STK_CSR & ~STK_CSR_CLKSOURCE) | + 8000a70: 6913 ldr r3, [r2, #16] + 8000a72: f023 0304 bic.w r3, r3, #4 + 8000a76: 4303 orrs r3, r0 + 8000a78: 6113 str r3, [r2, #16] +} + 8000a7a: 4770 bx lr + +08000a7c : + * + */ + +void systick_interrupt_enable(void) +{ + STK_CSR |= STK_CSR_TICKINT; + 8000a7c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 + 8000a80: 6913 ldr r3, [r2, #16] + 8000a82: f043 0302 orr.w r3, r3, #2 + 8000a86: 6113 str r3, [r2, #16] +} + 8000a88: 4770 bx lr + +08000a8a : + * + */ + +void systick_counter_enable(void) +{ + STK_CSR |= STK_CSR_ENABLE; + 8000a8a: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 + 8000a8e: 6913 ldr r3, [r2, #16] + 8000a90: f043 0301 orr.w r3, r3, #1 + 8000a94: 6113 str r3, [r2, #16] +} + 8000a96: 4770 bx lr + +08000a98 : + * The counter value is cleared. Useful for well defined startup. + */ + +void systick_clear(void) +{ + STK_CVR = 0; + 8000a98: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 + 8000a9c: 2200 movs r2, #0 + 8000a9e: 619a str r2, [r3, #24] +} + 8000aa0: 4770 bx lr + +08000aa2 : + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +void scb_set_priority_grouping(uint32_t prigroup) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; + 8000aa2: f040 60bf orr.w r0, r0, #100139008 @ 0x5f80000 + 8000aa6: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 + 8000aaa: f440 3000 orr.w r0, r0, #131072 @ 0x20000 + 8000aae: f8c3 0d0c str.w r0, [r3, #3340] @ 0xd0c +} + 8000ab2: 4770 bx lr + +08000ab4 : +void nvic_set_priority(uint8_t irqn, uint8_t priority) +{ + /* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the + * negative interrupt numbers assigned to the system interrupts. better + * handling would mean signed integers. */ + if (irqn >= NVIC_IRQ_COUNT) { + 8000ab4: 2895 cmp r0, #149 @ 0x95 + 8000ab6: d904 bls.n 8000ac2 + uint8_t shift = (irqn & 0x3) << 3; + uint8_t reg = irqn >> 2; + SCB_SHPR32(reg) = ((SCB_SHPR32(reg) & ~(0xFFUL << shift)) | + ((uint32_t) priority) << shift); +#else + SCB_SHPR((irqn & 0xF) - 4) = priority; + 8000ab8: f000 000f and.w r0, r0, #15 + 8000abc: 4b04 ldr r3, [pc, #16] @ (8000ad0 ) + 8000abe: 54c1 strb r1, [r0, r3] + 8000ac0: 4770 bx lr + uint8_t shift = (irqn & 0x3) << 3; + uint8_t reg = irqn >> 2; + NVIC_IPR32(reg) = ((NVIC_IPR32(reg) & ~(0xFFUL << shift)) | + ((uint32_t) priority) << shift); +#else + NVIC_IPR(irqn) = priority; + 8000ac2: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 + 8000ac6: f500 4064 add.w r0, r0, #58368 @ 0xe400 + 8000aca: 7001 strb r1, [r0, #0] +#endif + } +} + 8000acc: 4770 bx lr + 8000ace: bf00 nop + 8000ad0: e000ed14 .word 0xe000ed14 + +08000ad4 : + +#include + +void __attribute__((weak)) cm3_assert_failed(void) +{ + while (1); + 8000ad4: e7fe b.n 8000ad4 + ... + +08000ad8 : + +#include + +void flash_prefetch_enable(void) +{ + FLASH_ACR |= FLASH_ACR_PRFTEN; + 8000ad8: 4a02 ldr r2, [pc, #8] @ (8000ae4 ) + 8000ada: 6813 ldr r3, [r2, #0] + 8000adc: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8000ae0: 6013 str r3, [r2, #0] +} + 8000ae2: 4770 bx lr + 8000ae4: 52002000 .word 0x52002000 + +08000ae8 : + +void flash_prefetch_disable(void) +{ + FLASH_ACR &= ~FLASH_ACR_PRFTEN; + 8000ae8: 4a02 ldr r2, [pc, #8] @ (8000af4 ) + 8000aea: 6813 ldr r3, [r2, #0] + 8000aec: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8000af0: 6013 str r3, [r2, #0] +} + 8000af2: 4770 bx lr + 8000af4: 52002000 .word 0x52002000 + +08000af8 : + +void flash_set_ws(uint32_t ws) +{ + uint32_t reg32; + + reg32 = FLASH_ACR; + 8000af8: 4a03 ldr r2, [pc, #12] @ (8000b08 ) + 8000afa: 6813 ldr r3, [r2, #0] + reg32 &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_SHIFT); + 8000afc: f023 030f bic.w r3, r3, #15 + reg32 |= (ws << FLASH_ACR_LATENCY_SHIFT); + 8000b00: 4303 orrs r3, r0 + FLASH_ACR = reg32; + 8000b02: 6013 str r3, [r2, #0] +} + 8000b04: 4770 bx lr + 8000b06: bf00 nop + 8000b08: 52002000 .word 0x52002000 + +08000b0c : +#define DBGMCU_IDCODE_DEV_ID_STM32H7A3_B3_B0 0x480 + +void pwr_set_mode_ldo(void) { + /* Per table in manual for SMPS, mask and set SMPSEN=0 : LDOEN=1 : BYPASS=0. */ + const uint32_t cr3_mask = (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS); + PWR_CR3 = (PWR_CR3 & ~cr3_mask) | (PWR_CR3_LDOEN); + 8000b0c: 4a04 ldr r2, [pc, #16] @ (8000b20 ) + 8000b0e: f8d2 380c ldr.w r3, [r2, #2060] @ 0x80c + 8000b12: f023 0307 bic.w r3, r3, #7 + 8000b16: f043 0302 orr.w r3, r3, #2 + 8000b1a: f8c2 380c str.w r3, [r2, #2060] @ 0x80c +} + 8000b1e: 4770 bx lr + 8000b20: 58024000 .word 0x58024000 + +08000b24 : + +void pwr_set_mode_scu_ldo(void) { + const uint32_t cr3_mask = (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS); + PWR_CR3 = (PWR_CR3 & ~cr3_mask) | (PWR_CR3_SCUEN | PWR_CR3_LDOEN); + 8000b24: 4a04 ldr r2, [pc, #16] @ (8000b38 ) + 8000b26: f8d2 380c ldr.w r3, [r2, #2060] @ 0x80c + 8000b2a: f023 0307 bic.w r3, r3, #7 + 8000b2e: f043 0306 orr.w r3, r3, #6 + 8000b32: f8c2 380c str.w r3, [r2, #2060] @ 0x80c +} + 8000b36: 4770 bx lr + 8000b38: 58024000 .word 0x58024000 + +08000b3c : + +void pwr_set_mode_smps_ldo(bool supply_external, uint32_t smps_level, bool use_ldo) { + 8000b3c: b508 push {r3, lr} + uint32_t cr3_mask, cr3_set; + cr3_mask = (PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS); + cr3_mask |= PWR_CR3_SMPSLEVEL_MASK << PWR_CR3_SMPSLEVEL_SHIFT; + + /* Default, take in unconditional settings, will OR in the rest. */ + cr3_set = PWR_CR3_SMPSEN | (smps_level << PWR_CR3_SMPSLEVEL_SHIFT); + 8000b3e: 010b lsls r3, r1, #4 + if (supply_external) { + 8000b40: b970 cbnz r0, 8000b60 + cr3_set = PWR_CR3_SMPSEN | (smps_level << PWR_CR3_SMPSLEVEL_SHIFT); + 8000b42: f043 0304 orr.w r3, r3, #4 + } + + if (use_ldo) { + cr3_set |= PWR_CR3_LDOEN; + } + PWR_CR3 = (PWR_CR3 & ~cr3_mask) | cr3_set; + 8000b46: 4809 ldr r0, [pc, #36] @ (8000b6c ) + if (use_ldo) { + 8000b48: 4252 negs r2, r2 + PWR_CR3 = (PWR_CR3 & ~cr3_mask) | cr3_set; + 8000b4a: f8d0 180c ldr.w r1, [r0, #2060] @ 0x80c + if (use_ldo) { + 8000b4e: f002 0202 and.w r2, r2, #2 + PWR_CR3 = (PWR_CR3 & ~cr3_mask) | cr3_set; + 8000b52: f021 013f bic.w r1, r1, #63 @ 0x3f + 8000b56: 430a orrs r2, r1 + 8000b58: 431a orrs r2, r3 + 8000b5a: f8c0 280c str.w r2, [r0, #2060] @ 0x80c +} + 8000b5e: bd08 pop {r3, pc} + cm3_assert(smps_level != PWR_CR3_SMPSLEVEL_VOS); /* Unsupported setting! */ + 8000b60: b909 cbnz r1, 8000b66 + 8000b62: f7ff ffb7 bl 8000ad4 + cr3_set |= PWR_CR3_SMPSEXTHP; + 8000b66: f043 030c orr.w r3, r3, #12 + 8000b6a: e7ec b.n 8000b46 + 8000b6c: 58024000 .word 0x58024000 + +08000b70 : + +void pwr_set_mode_bypass(void) { + const uint32_t cr3_mask = (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS); + PWR_CR3 = (PWR_CR3 & ~cr3_mask) | PWR_CR3_BYPASS; + 8000b70: 4a04 ldr r2, [pc, #16] @ (8000b84 ) + 8000b72: f8d2 380c ldr.w r3, [r2, #2060] @ 0x80c + 8000b76: f023 0307 bic.w r3, r3, #7 + 8000b7a: f043 0301 orr.w r3, r3, #1 + 8000b7e: f8c2 380c str.w r3, [r2, #2060] @ 0x80c +} + 8000b82: 4770 bx lr + 8000b84: 58024000 .word 0x58024000 + +08000b88 : + +void pwr_set_mode_scu_bypass(void) { + const uint32_t cr3_mask = (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS); + PWR_CR3 = (PWR_CR3 & ~cr3_mask) | (PWR_CR3_SCUEN | PWR_CR3_BYPASS); + 8000b88: 4a04 ldr r2, [pc, #16] @ (8000b9c ) + 8000b8a: f8d2 380c ldr.w r3, [r2, #2060] @ 0x80c + 8000b8e: f023 0307 bic.w r3, r3, #7 + 8000b92: f043 0305 orr.w r3, r3, #5 + 8000b96: f8c2 380c str.w r3, [r2, #2060] @ 0x80c +} + 8000b9a: 4770 bx lr + 8000b9c: 58024000 .word 0x58024000 + +08000ba0 : + + +void pwr_set_mode(enum pwr_sys_mode mode, uint8_t smps_level) { + 8000ba0: b508 push {r3, lr} + switch (mode) { + 8000ba2: 2807 cmp r0, #7 + 8000ba4: d807 bhi.n 8000bb6 + 8000ba6: e8df f000 tbb [pc, r0] + 8000baa: 0c04 .short 0x0c04 + 8000bac: 1d12120f .word 0x1d12120f + 8000bb0: 211d .short 0x211d + case PWR_SYS_SCU_LDO: + pwr_set_mode_scu_ldo(); + 8000bb2: f7ff ffb7 bl 8000b24 + case PWR_SYS_BYPASS: + pwr_set_mode_bypass(); + break; + } + /* Wait for power supply status to state ready. */ + while (!(PWR_CSR1 & PWR_CSR1_ACTVOSRDY)); + 8000bb6: 4a0f ldr r2, [pc, #60] @ (8000bf4 ) + 8000bb8: f8d2 3804 ldr.w r3, [r2, #2052] @ 0x804 + 8000bbc: 049b lsls r3, r3, #18 + 8000bbe: d5fb bpl.n 8000bb8 +} + 8000bc0: bd08 pop {r3, pc} + pwr_set_mode_scu_bypass(); + 8000bc2: f7ff ffe1 bl 8000b88 + break; + 8000bc6: e7f6 b.n 8000bb6 + pwr_set_mode_ldo(); + 8000bc8: f7ff ffa0 bl 8000b0c + break; + 8000bcc: e7f3 b.n 8000bb6 + pwr_set_mode_smps_ldo(false, PWR_CR3_SMPSLEVEL_VOS, mode == PWR_SYS_SMPS_LDO); + 8000bce: f1a0 0c04 sub.w ip, r0, #4 + 8000bd2: 2100 movs r1, #0 + 8000bd4: f1dc 0200 rsbs r2, ip, #0 + 8000bd8: eb42 020c adc.w r2, r2, ip + pwr_set_mode_smps_ldo(false, smps_level, mode == PWR_SYS_EXT_SMPS_LDO); + 8000bdc: 2000 movs r0, #0 + 8000bde: f7ff ffad bl 8000b3c + break; + 8000be2: e7e8 b.n 8000bb6 + pwr_set_mode_smps_ldo(false, smps_level, mode == PWR_SYS_EXT_SMPS_LDO); + 8000be4: 3805 subs r0, #5 + 8000be6: 4242 negs r2, r0 + 8000be8: 4142 adcs r2, r0 + 8000bea: e7f7 b.n 8000bdc + pwr_set_mode_bypass(); + 8000bec: f7ff ffc0 bl 8000b70 + break; + 8000bf0: e7e1 b.n 8000bb6 + 8000bf2: bf00 nop + 8000bf4: 58024000 .word 0x58024000 + +08000bf8 : + uint32_t pwr_cr1_reg = PWR_CR1; + pwr_cr1_reg = (pwr_cr1_reg & ~(PWR_CR1_SVOS_MASK << PWR_CR1_SVOS_SHIFT)); + PWR_CR1 = pwr_cr1_reg | scale; +} + +void pwr_set_vos_scale(enum pwr_vos_scale scale) { + 8000bf8: b5f8 push {r3, r4, r5, r6, r7, lr} + PWR_D3CR_VOS_SCALE_0, + PWR_D3CR_VOS_SCALE_1, + PWR_D3CR_VOS_SCALE_2, + PWR_D3CR_VOS_SCALE_3, + }; + cm3_assert(scale != PWR_VOS_SCALE_UNDEFINED); /* Make sure this has been set. */ + 8000bfa: 4607 mov r7, r0 + 8000bfc: b908 cbnz r0, 8000c02 + 8000bfe: f7ff ff69 bl 8000ad4 + + /* "SmartRun Domain" devices (presently only know of A3/B3/B0) have different mapping. + * Note: DBGMCU_IDCODE_DEV_ID_STM32H7A3 covers all three of these models. + */ + uint32_t devid = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK; + 8000c02: 4b20 ldr r3, [pc, #128] @ (8000c84 ) + if (devid == DBGMCU_IDCODE_DEV_ID_STM32H7A3_B3_B0) { + const uint32_t srdcr_vos_mask = (PWR_SRDCR_VOS_MASK << PWR_SRDCR_VOS_SHIFT); + const uint32_t vos_value = srdcr_vos_values[scale - 1] << PWR_SRDCR_VOS_SHIFT; + 8000c04: 1e42 subs r2, r0, #1 + 8000c06: 4e20 ldr r6, [pc, #128] @ (8000c88 ) + uint32_t devid = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK; + 8000c08: 681b ldr r3, [r3, #0] + 8000c0a: f3c3 030b ubfx r3, r3, #0, #12 + if (devid == DBGMCU_IDCODE_DEV_ID_STM32H7A3_B3_B0) { + 8000c0e: f5b3 6f90 cmp.w r3, #1152 @ 0x480 + 8000c12: d10f bne.n 8000c34 + PWR_SRDCR = (PWR_SRDCR & ~srdcr_vos_mask) | vos_value; + 8000c14: f8d6 3818 ldr.w r3, [r6, #2072] @ 0x818 + const uint32_t vos_value = srdcr_vos_values[scale - 1] << PWR_SRDCR_VOS_SHIFT; + 8000c18: 491c ldr r1, [pc, #112] @ (8000c8c ) + PWR_SRDCR = (PWR_SRDCR & ~srdcr_vos_mask) | vos_value; + 8000c1a: f423 4340 bic.w r3, r3, #49152 @ 0xc000 + const uint32_t vos_value = srdcr_vos_values[scale - 1] << PWR_SRDCR_VOS_SHIFT; + 8000c1e: 5c8a ldrb r2, [r1, r2] + PWR_SRDCR = (PWR_SRDCR & ~srdcr_vos_mask) | vos_value; + 8000c20: ea43 3382 orr.w r3, r3, r2, lsl #14 + 8000c24: f8c6 3818 str.w r3, [r6, #2072] @ 0x818 + } + } else { + PWR_D3CR = d3cr_masked | d3cr_vos; + } + } + while (!(PWR_D3CR & PWR_D3CR_VOSRDY)); /* VOSRDY bit is same between D3CR and SRDCR. */ + 8000c28: 4a17 ldr r2, [pc, #92] @ (8000c88 ) + 8000c2a: f8d2 3818 ldr.w r3, [r2, #2072] @ 0x818 + 8000c2e: 049b lsls r3, r3, #18 + 8000c30: d5fb bpl.n 8000c2a +} + 8000c32: bdf8 pop {r3, r4, r5, r6, r7, pc} + uint32_t d3cr_vos = (uint32_t)d3cr_vos_values[scale - 1] << PWR_D3CR_VOS_SHIFT; + 8000c34: 4916 ldr r1, [pc, #88] @ (8000c90 ) + if (devid == DBGMCU_IDCODE_DEV_ID_STM32H74X_5X) { + 8000c36: f5b3 6f8a cmp.w r3, #1104 @ 0x450 + uint32_t d3cr_masked = PWR_D3CR & ~(PWR_D3CR_VOS_MASK << PWR_D3CR_VOS_SHIFT); + 8000c3a: f8d6 5818 ldr.w r5, [r6, #2072] @ 0x818 + uint32_t d3cr_vos = (uint32_t)d3cr_vos_values[scale - 1] << PWR_D3CR_VOS_SHIFT; + 8000c3e: 5c8c ldrb r4, [r1, r2] + uint32_t d3cr_masked = PWR_D3CR & ~(PWR_D3CR_VOS_MASK << PWR_D3CR_VOS_SHIFT); + 8000c40: f425 4540 bic.w r5, r5, #49152 @ 0xc000 + uint32_t d3cr_vos = (uint32_t)d3cr_vos_values[scale - 1] << PWR_D3CR_VOS_SHIFT; + 8000c44: ea4f 3484 mov.w r4, r4, lsl #14 + if (devid == DBGMCU_IDCODE_DEV_ID_STM32H74X_5X) { + 8000c48: d118 bne.n 8000c7c + rcc_periph_clock_enable(RCC_SYSCFG); /* Ensure we can access ODEN. */ + 8000c4a: f641 6081 movw r0, #7809 @ 0x1e81 + 8000c4e: f7ff fea5 bl 800099c + if (scale == PWR_VOS_SCALE_0) { + 8000c52: 2f01 cmp r7, #1 + 8000c54: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000c58: d10a bne.n 8000c70 + PWR_D3CR = d3cr_masked | (PWR_D3CR_VOS_SCALE_1 << PWR_SRDCR_VOS_SHIFT); + 8000c5a: f445 4540 orr.w r5, r5, #49152 @ 0xc000 + 8000c5e: f8c6 5818 str.w r5, [r6, #2072] @ 0x818 + SYSCFG_PWRCR |= SYSCFG_PWRCR_ODEN; + 8000c62: f8d3 242c ldr.w r2, [r3, #1068] @ 0x42c + 8000c66: f042 0201 orr.w r2, r2, #1 + 8000c6a: f8c3 242c str.w r2, [r3, #1068] @ 0x42c + 8000c6e: e7db b.n 8000c28 + SYSCFG_PWRCR &= ~SYSCFG_PWRCR_ODEN; + 8000c70: f8d3 242c ldr.w r2, [r3, #1068] @ 0x42c + 8000c74: f022 0201 bic.w r2, r2, #1 + 8000c78: f8c3 242c str.w r2, [r3, #1068] @ 0x42c + PWR_D3CR = d3cr_masked | d3cr_vos; + 8000c7c: 432c orrs r4, r5 + 8000c7e: f8c6 4818 str.w r4, [r6, #2072] @ 0x818 + 8000c82: e7d1 b.n 8000c28 + 8000c84: 5c001000 .word 0x5c001000 + 8000c88: 58024000 .word 0x58024000 + 8000c8c: 08000d34 .word 0x08000d34 + 8000c90: 08000d30 .word 0x08000d30 + +08000c94 : + 8000c94: 0783 lsls r3, r0, #30 + 8000c96: b530 push {r4, r5, lr} + 8000c98: d046 beq.n 8000d28 + 8000c9a: 1884 adds r4, r0, r2 + 8000c9c: 4684 mov ip, r0 + 8000c9e: e004 b.n 8000caa + 8000ca0: f803 1b01 strb.w r1, [r3], #1 + 8000ca4: 079d lsls r5, r3, #30 + 8000ca6: d004 beq.n 8000cb2 + 8000ca8: 469c mov ip, r3 + 8000caa: 45a4 cmp ip, r4 + 8000cac: 4663 mov r3, ip + 8000cae: d1f7 bne.n 8000ca0 + 8000cb0: bd30 pop {r4, r5, pc} + 8000cb2: 3a01 subs r2, #1 + 8000cb4: 4402 add r2, r0 + 8000cb6: eba2 020c sub.w r2, r2, ip + 8000cba: 2a03 cmp r2, #3 + 8000cbc: d929 bls.n 8000d12 + 8000cbe: b2cc uxtb r4, r1 + 8000cc0: eb04 2404 add.w r4, r4, r4, lsl #8 + 8000cc4: 2a0f cmp r2, #15 + 8000cc6: eb04 4404 add.w r4, r4, r4, lsl #16 + 8000cca: d92f bls.n 8000d2c + 8000ccc: f1a2 0c10 sub.w ip, r2, #16 + 8000cd0: f02c 0c0f bic.w ip, ip, #15 + 8000cd4: f103 0510 add.w r5, r3, #16 + 8000cd8: 44ac add ip, r5 + 8000cda: e9c3 4400 strd r4, r4, [r3] + 8000cde: e9c3 4402 strd r4, r4, [r3, #8] + 8000ce2: 3310 adds r3, #16 + 8000ce4: 4563 cmp r3, ip + 8000ce6: d1f8 bne.n 8000cda + 8000ce8: f012 0f0c tst.w r2, #12 + 8000cec: f002 0e0f and.w lr, r2, #15 + 8000cf0: d018 beq.n 8000d24 + 8000cf2: f02e 0c03 bic.w ip, lr, #3 + 8000cf6: 449c add ip, r3 + 8000cf8: f1ae 0504 sub.w r5, lr, #4 + 8000cfc: 461a mov r2, r3 + 8000cfe: f842 4b04 str.w r4, [r2], #4 + 8000d02: 4562 cmp r2, ip + 8000d04: d1fb bne.n 8000cfe + 8000d06: f025 0403 bic.w r4, r5, #3 + 8000d0a: 3304 adds r3, #4 + 8000d0c: f00e 0203 and.w r2, lr, #3 + 8000d10: 4423 add r3, r4 + 8000d12: 2a00 cmp r2, #0 + 8000d14: d0cc beq.n 8000cb0 + 8000d16: b2c9 uxtb r1, r1 + 8000d18: 441a add r2, r3 + 8000d1a: f803 1b01 strb.w r1, [r3], #1 + 8000d1e: 4293 cmp r3, r2 + 8000d20: d1fb bne.n 8000d1a + 8000d22: bd30 pop {r4, r5, pc} + 8000d24: 4672 mov r2, lr + 8000d26: e7f4 b.n 8000d12 + 8000d28: 4603 mov r3, r0 + 8000d2a: e7c6 b.n 8000cba + 8000d2c: 4696 mov lr, r2 + 8000d2e: e7e0 b.n 8000cf2 + +08000d30 : + 8000d30: 0300 0102 .... + +08000d34 : + 8000d34: 0203 0001 .... diff --git a/1gpio/bin/gpio.map b/1gpio/bin/gpio.map new file mode 100644 index 0000000..e78e7a5 --- /dev/null +++ b/1gpio/bin/gpio.map @@ -0,0 +1,1018 @@ +Archive member included to satisfy reference by file (symbol) + +../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + build/.objs/gpio/linux/arm32/release/user/src/main.c.o (gpio_set) +../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o (gpio_mode_setup) +../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + build/.objs/gpio/linux/arm32/release/user/src/main.c.o (rcc_clock_setup_pll) +../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o (rcc_periph_clock_enable) +../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + (reset_handler) +../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + build/.objs/gpio/linux/arm32/release/user/src/systick.c.o (systick_set_reload) +../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + build/.objs/gpio/linux/arm32/release/user/src/main.c.o (scb_set_priority_grouping) +../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + build/.objs/gpio/linux/arm32/release/user/src/systick.c.o (nvic_set_priority) +../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) (cm3_assert_failed) +../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) (flash_prefetch_enable) +../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) (pwr_set_mode) +/home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a(libc_a-memset.o) + build/.objs/gpio/linux/arm32/release/user/src/main.c.o (memset) + +Discarded input sections + + .data 0x00000000 0x0 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .bss 0x00000000 0x0 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .data 0x00000000 0x0 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .bss 0x00000000 0x0 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .data 0x00000000 0x0 build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .text.gpio_port_read + 0x00000000 0x6 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .text.gpio_port_write + 0x00000000 0x4 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .text.gpio_port_config_lock + 0x00000000 0x10 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .text.gpio_set_af + 0x00000000 0x58 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0x2ce ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0x37e ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x00000000 0xca ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_get_usart_clk_freq + 0x00000000 0x70 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_get_timer_clk_freq + 0x00000000 0x38 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_get_i2c_clk_freq + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_get_spi_clk_freq + 0x00000000 0x90 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_get_fdcan_clk_freq + 0x00000000 0x44 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_set_peripheral_clk_sel + 0x00000000 0xc8 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_set_fdcan_clksel + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_set_rng_clksel + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_set_spi123_clksel + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_set_spi45_clksel + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00000000 0x2ce ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_peripheral_enable_clock + 0x00000000 0x8 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_peripheral_disable_clock + 0x00000000 0xa ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_peripheral_reset + 0x00000000 0x8 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_peripheral_clear_reset + 0x00000000 0xa ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_periph_clock_disable + 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_periph_reset_pulse + 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_periph_reset_hold + 0x00000000 0x4 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_periph_reset_release + 0x00000000 0x4 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_set_mco + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_osc_bypass_enable + 0x00000000 0x30 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_osc_bypass_disable + 0x00000000 0x30 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .text.rcc_get_div_from_hpre + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0x2ce ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0x1d4 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x00000000 0x7cc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text.systick_get_reload + 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text.systick_get_value + 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text.systick_set_frequency + 0x00000000 0x38 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text.systick_interrupt_disable + 0x00000000 0xe ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text.systick_counter_disable + 0x00000000 0xe ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text.systick_get_countflag + 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .text.systick_get_calib + 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .text.scb_reset_core + 0x00000000 0x10 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .text.scb_reset_system + 0x00000000 0x10 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00000000 0x452 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_enable_irq + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_disable_irq + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_get_pending_irq + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_set_pending_irq + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_clear_pending_irq + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_get_irq_enabled + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_get_active_irq + 0x00000000 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .text.nvic_generate_software_interrupt + 0x00000000 0x14 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00000000 0x3b5 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .text.cm3_assert_failed_verbose + 0x00000000 0x6 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_macro 0x00000000 0x16 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .text.flash_unlock_option_bytes + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x2ce ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x143 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x00000000 0x46 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .group 0x00000000 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .text 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .data 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .bss 0x00000000 0x0 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .text.pwr_set_svos_scale + 0x00000000 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0x16 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0x2ce ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00000000 0x1d4 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .text 0x00000000 0x0 /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a(libc_a-memset.o) + .data 0x00000000 0x0 /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a(libc_a-memset.o) + .bss 0x00000000 0x0 /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a(libc_a-memset.o) + +Memory Configuration + +Name Origin Length Attributes +rom 0x08000000 0x00200000 xr +ram 0x20000000 0x00020000 xrw +ram2 0x24000000 0x00080000 xrw +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o +LOAD build/.objs/gpio/linux/arm32/release/user/src/main.c.o +LOAD build/.objs/gpio/linux/arm32/release/user/src/systick.c.o +LOAD ../../libopencm3/lib/libopencm3_stm32h7.a +LOAD /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+dp/hard/libgcc.a +LOAD /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a +LOAD /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libstdc++.a +LOAD /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libm.a +LOAD /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a +START GROUP +LOAD /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v7e-m+dp/hard/libgcc.a +LOAD /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a +END GROUP + +.text 0x08000000 0xd38 + *(.vectors) + .vectors 0x08000000 0x298 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + 0x08000000 vector_table + *(.text*) + .text 0x08000298 0x60 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + 0x08000298 user_gpio_setup + .text 0x080002f8 0x15c build/.objs/gpio/linux/arm32/release/user/src/main.c.o + 0x080002f8 main + .text 0x08000454 0x90 build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + 0x08000454 user_delay_ms + 0x08000488 systick_init + 0x080004c8 sys_tick_handler + .text.gpio_set + 0x080004e4 0x4 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + 0x080004e4 gpio_set + .text.gpio_clear + 0x080004e8 0x6 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + 0x080004e8 gpio_clear + .text.gpio_get + 0x080004ee 0x6 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + 0x080004ee gpio_get + .text.gpio_toggle + 0x080004f4 0x12 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + 0x080004f4 gpio_toggle + .text.gpio_mode_setup + 0x08000506 0x40 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + 0x08000506 gpio_mode_setup + .text.gpio_set_output_options + 0x08000546 0x36 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + 0x08000546 gpio_set_output_options + .text.rcc_configure_pll + 0x0800057c 0x18c ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .text.rcc_clock_setup_pll + 0x08000708 0x218 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + 0x08000708 rcc_clock_setup_pll + .text.rcc_get_bus_clk_freq + 0x08000920 0x7c ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + 0x08000920 rcc_get_bus_clk_freq + .text.rcc_periph_clock_enable + 0x0800099c 0x1a ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + 0x0800099c rcc_periph_clock_enable + .text.blocking_handler + 0x080009b6 0x2 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + 0x080009b6 i2c4_ev_isr + 0x080009b6 tim8_brk_tim12_isr + 0x080009b6 ltdc_isr + 0x080009b6 usart3_isr + 0x080009b6 swpmi1_isr + 0x080009b6 tim7_isr + 0x080009b6 dma2d_isr + 0x080009b6 bdma_ch5_isr + 0x080009b6 lptim4_isr + 0x080009b6 adc1_2_isr + 0x080009b6 uart8_isr + 0x080009b6 crs_isr + 0x080009b6 dma1_str5_isr + 0x080009b6 hrtim1_timc_isr + 0x080009b6 i2c4_er_isr + 0x080009b6 otg_hs_isr + 0x080009b6 blocking_handler + 0x080009b6 tim5_isr + 0x080009b6 rtc_wkup_isr + 0x080009b6 cec_isr + 0x080009b6 otg_fs_isr + 0x080009b6 spi1_isr + 0x080009b6 dma2_str2_isr + 0x080009b6 i2c3_er_isr + 0x080009b6 jpeg_isr + 0x080009b6 exti2_isr + 0x080009b6 fdcan_cal_isr + 0x080009b6 spi5_isr + 0x080009b6 mdios_isr + 0x080009b6 dmamux2_ovr_isr + 0x080009b6 tim17_isr + 0x080009b6 cm7_sev_isr + 0x080009b6 fdcan2_it0_isr + 0x080009b6 reserved8_isr + 0x080009b6 wkup_isr + 0x080009b6 tamp_stamp_isr + 0x080009b6 usart1_isr + 0x080009b6 i2c3_ev_isr + 0x080009b6 usage_fault_handler + 0x080009b6 dfsdm1_it2_isr + 0x080009b6 bdma_ch6_isr + 0x080009b6 reserved4_isr + 0x080009b6 tim1_cc_isr + 0x080009b6 reserved5_isr + 0x080009b6 tim1_up_tim10_isr + 0x080009b6 reserved7_isr + 0x080009b6 eth_isr + 0x080009b6 hrtim1_flt_isr + 0x080009b6 otg_fs_wkup_isr + 0x080009b6 tim16_isr + 0x080009b6 spi6_isr + 0x080009b6 pvd_isr + 0x080009b6 mdma_isr + 0x080009b6 lpuart_isr + 0x080009b6 bdma_ch3_isr + 0x080009b6 fdcan1_it0_isr + 0x080009b6 dfsdm1_it1_isr + 0x080009b6 dma2_str3_isr + 0x080009b6 sai3_isr + 0x080009b6 dma2_str4_isr + 0x080009b6 dma2_str6_isr + 0x080009b6 rcc_isr + 0x080009b6 lp_tim1_isr + 0x080009b6 reserved3_isr + 0x080009b6 flash_isr + 0x080009b6 uart4_isr + 0x080009b6 rtc_alarm_isr + 0x080009b6 exti15_10_isr + 0x080009b6 hash_rng_isr + 0x080009b6 bdma_ch7_isr + 0x080009b6 tim1_trg_com_tim11_isr + 0x080009b6 hard_fault_handler + 0x080009b6 exti1_isr + 0x080009b6 dma1_str4_isr + 0x080009b6 i2c1_ev_isr + 0x080009b6 usart6_isr + 0x080009b6 dfsdm1_it0_isr + 0x080009b6 bdma_ch2_isr + 0x080009b6 hrtim1_timb_isr + 0x080009b6 sdmmc2_isr + 0x080009b6 spi2_isr + 0x080009b6 cryp_isr + 0x080009b6 dma1_str1_isr + 0x080009b6 hrtim1_tima_isr + 0x080009b6 tim15_isr + 0x080009b6 wwdg1_rst_isr + 0x080009b6 exti3_isr + 0x080009b6 adc3_isr + 0x080009b6 tim3_isr + 0x080009b6 usart2_isr + 0x080009b6 sai1_isr + 0x080009b6 fpu_isr + 0x080009b6 i2c2_er_isr + 0x080009b6 dma2_str0_isr + 0x080009b6 dma1_str6_isr + 0x080009b6 hrtim1_timd_isr + 0x080009b6 reserved2_isr + 0x080009b6 otg_fs_ep1_out_isr + 0x080009b6 i2c2_ev_isr + 0x080009b6 uart5_isr + 0x080009b6 dfsdm1_it3_isr + 0x080009b6 reserved1_isr + 0x080009b6 spi4_isr + 0x080009b6 tim8_up_tim13_isr + 0x080009b6 fsmc_isr + 0x080009b6 exti4_isr + 0x080009b6 tim6_dac_isr + 0x080009b6 spdifrx_isr + 0x080009b6 bdma_ch4_isr + 0x080009b6 tim8_trg_com_tim14_isr + 0x080009b6 comp_isr + 0x080009b6 mem_manage_handler + 0x080009b6 lptim2_isr + 0x080009b6 fdcan1_it1_isr + 0x080009b6 reserved6_isr + 0x080009b6 exti9_5_isr + 0x080009b6 dma1_str3_isr + 0x080009b6 ramecc1_isr + 0x080009b6 tim1_brk_tim9_isr + 0x080009b6 uart7_isr + 0x080009b6 hsem0_isr + 0x080009b6 hrtim1_mst_isr + 0x080009b6 dma2_str5_isr + 0x080009b6 tim4_isr + 0x080009b6 mdios_wkup_isr + 0x080009b6 sai2_isr + 0x080009b6 lptim3_isr + 0x080009b6 otg_hs_wkup_isr + 0x080009b6 i2c1_er_isr + 0x080009b6 dmamux1_ov_isr + 0x080009b6 hrtim1_time_isr + 0x080009b6 fdcan2_it1_isr + 0x080009b6 bdma_ch1_isr + 0x080009b6 tim8_cc_isr + 0x080009b6 dma2_str1_isr + 0x080009b6 dma1_str0_isr + 0x080009b6 dcmi_isr + 0x080009b6 lptim5_isr + 0x080009b6 bdma_ch0_isr + 0x080009b6 ltdc_er_isr + 0x080009b6 dma1_str7_isr + 0x080009b6 eth_wkup_isr + 0x080009b6 sai4_isr + 0x080009b6 bus_fault_handler + 0x080009b6 wwdg_isr + 0x080009b6 otg_hs_ep1_out_isr + 0x080009b6 otg_fs_ep1_in_isr + 0x080009b6 sdmmc1_isr + 0x080009b6 spi3_isr + 0x080009b6 quadspi_isr + 0x080009b6 otg_hs_ep1_in_isr + 0x080009b6 dma1_str2_isr + 0x080009b6 tim2_isr + 0x080009b6 exti0_isr + 0x080009b6 dma2_str7_isr + .text.null_handler + 0x080009b8 0x2 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + 0x080009b8 null_handler + 0x080009b8 sv_call_handler + 0x080009b8 pend_sv_handler + 0x080009b8 debug_monitor_handler + 0x080009b8 nmi_handler + *fill* 0x080009ba 0x2 + .text.reset_handler + 0x080009bc 0xa0 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + 0x080009bc reset_handler + .text.systick_set_reload + 0x08000a5c 0xc ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + 0x08000a5c systick_set_reload + .text.systick_set_clocksource + 0x08000a68 0x14 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + 0x08000a68 systick_set_clocksource + .text.systick_interrupt_enable + 0x08000a7c 0xe ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + 0x08000a7c systick_interrupt_enable + .text.systick_counter_enable + 0x08000a8a 0xe ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + 0x08000a8a systick_counter_enable + .text.systick_clear + 0x08000a98 0xa ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + 0x08000a98 systick_clear + .text.scb_set_priority_grouping + 0x08000aa2 0x12 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + 0x08000aa2 scb_set_priority_grouping + .text.nvic_set_priority + 0x08000ab4 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + 0x08000ab4 nvic_set_priority + .text.cm3_assert_failed + 0x08000ad4 0x2 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + 0x08000ad4 cm3_assert_failed + *fill* 0x08000ad6 0x2 + .text.flash_prefetch_enable + 0x08000ad8 0x10 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + 0x08000ad8 flash_prefetch_enable + .text.flash_prefetch_disable + 0x08000ae8 0x10 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + 0x08000ae8 flash_prefetch_disable + .text.flash_set_ws + 0x08000af8 0x14 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + 0x08000af8 flash_set_ws + .text.pwr_set_mode_ldo + 0x08000b0c 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000b0c pwr_set_mode_ldo + .text.pwr_set_mode_scu_ldo + 0x08000b24 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000b24 pwr_set_mode_scu_ldo + .text.pwr_set_mode_smps_ldo + 0x08000b3c 0x34 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000b3c pwr_set_mode_smps_ldo + .text.pwr_set_mode_bypass + 0x08000b70 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000b70 pwr_set_mode_bypass + .text.pwr_set_mode_scu_bypass + 0x08000b88 0x18 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000b88 pwr_set_mode_scu_bypass + .text.pwr_set_mode + 0x08000ba0 0x58 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000ba0 pwr_set_mode + .text.pwr_set_vos_scale + 0x08000bf8 0x9c ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000bf8 pwr_set_vos_scale + .text.memset 0x08000c94 0x9c /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a(libc_a-memset.o) + 0x08000c94 memset + 0x08000d30 . = ALIGN (0x4) + *(.rodata*) + .rodata.d3cr_vos_values.0 + 0x08000d30 0x4 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .rodata.srdcr_vos_values.1 + 0x08000d34 0x4 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + 0x08000d38 . = ALIGN (0x4) + +.glue_7 0x08000d38 0x0 + .glue_7 0x08000d38 0x0 linker stubs + +.glue_7t 0x08000d38 0x0 + .glue_7t 0x08000d38 0x0 linker stubs + +.vfp11_veneer 0x08000d38 0x0 + .vfp11_veneer 0x08000d38 0x0 linker stubs + +.v4_bx 0x08000d38 0x0 + .v4_bx 0x08000d38 0x0 linker stubs + +.iplt 0x08000d38 0x0 + .iplt 0x08000d38 0x0 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + +.rel.dyn 0x08000d38 0x0 + .rel.iplt 0x08000d38 0x0 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + +.preinit_array 0x08000d38 0x0 + 0x08000d38 . = ALIGN (0x4) + 0x08000d38 __preinit_array_start = . + *(.preinit_array) + 0x08000d38 __preinit_array_end = . + +.init_array 0x08000d38 0x0 + 0x08000d38 . = ALIGN (0x4) + 0x08000d38 __init_array_start = . + *(SORT_BY_NAME(.init_array.*)) + *(.init_array) + 0x08000d38 __init_array_end = . + +.fini_array 0x08000d38 0x0 + 0x08000d38 . = ALIGN (0x4) + 0x08000d38 __fini_array_start = . + *(.fini_array) + *(SORT_BY_NAME(.fini_array.*)) + 0x08000d38 __fini_array_end = . + +.ARM.extab + *(.ARM.extab*) + +.ARM.exidx 0x08000d38 0x0 + 0x08000d38 __exidx_start = . + *(.ARM.exidx*) + 0x08000d38 __exidx_end = . + 0x08000d38 . = ALIGN (0x4) + 0x08000d38 _etext = . + +.noinit + *(.noinit*) + 0x08000d38 . = ALIGN (0x4) + +.data 0x20000000 0x24 load address 0x08000d38 + 0x20000000 _data = . + *(.data*) + .data.rcc_clock_tree + 0x20000000 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + *(.ramtext*) + 0x20000024 . = ALIGN (0x4) + *fill* 0x20000022 0x2 + 0x20000024 _edata = . + 0x08000d38 _data_loadaddr = LOADADDR (.data) + +.igot.plt 0x20000024 0x0 load address 0x08000d5c + .igot.plt 0x20000024 0x0 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + +.bss 0x20000024 0x4 load address 0x08000d5c + *(.bss*) + .bss 0x20000024 0x4 build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + 0x20000024 systick + *(COMMON) + 0x20000028 . = ALIGN (0x4) + 0x20000028 _ebss = . + +/DISCARD/ + *(.eh_frame) + +.heap 0x24000000 0x80000 + 0x24000000 _sheap = . + 0x24080000 . = (ORIGIN (ram2) + LENGTH (ram2)) + *fill* 0x24000000 0x80000 + 0x24080000 _eheap = . + 0x24080000 . = ALIGN (0x4) + 0x24080000 end = . + 0x20020000 PROVIDE (_stack = (ORIGIN (ram) + LENGTH (ram))) + [!provide] PROVIDE (_sheap = ORIGIN (ram2)) + [!provide] PROVIDE (_eheap = (ORIGIN (ram2) + LENGTH (ram2))) +OUTPUT(/home/time/doc/codefile/embe/Blog/stm32/stm32h7/1gpio/bin/gpio.elf elf32-littlearm) +LOAD linker stubs + +.debug_info 0x00000000 0x341d + .debug_info 0x00000000 0x3f0 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .debug_info 0x000003f0 0x682 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .debug_info 0x00000a72 0x1f2 build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .debug_info 0x00000c64 0x23a ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_info 0x00000e9e 0x1f4 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_info 0x00001092 0xaf3 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_info 0x00001b85 0x803 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_info 0x00002388 0x2cd ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_info 0x00002655 0x26d ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_info 0x000028c2 0xcf ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_info 0x00002991 0x212 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_info 0x00002ba3 0x101 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_info 0x00002ca4 0xe5 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_info 0x00002d89 0x694 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.debug_abbrev 0x00000000 0x10fd + .debug_abbrev 0x00000000 0xa4 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .debug_abbrev 0x000000a4 0x16c build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .debug_abbrev 0x00000210 0x16d build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .debug_abbrev 0x0000037d 0x117 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_abbrev 0x00000494 0xc3 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_abbrev 0x00000557 0x36a ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_abbrev 0x000008c1 0x186 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_abbrev 0x00000a47 0x15f ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_abbrev 0x00000ba6 0x156 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_abbrev 0x00000cfc 0x88 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_abbrev 0x00000d84 0xb7 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_abbrev 0x00000e3b 0x94 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_abbrev 0x00000ecf 0x96 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_abbrev 0x00000f65 0x198 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.debug_aranges 0x00000000 0x3d0 + .debug_aranges + 0x00000000 0x20 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .debug_aranges + 0x00000020 0x20 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .debug_aranges + 0x00000040 0x20 build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .debug_aranges + 0x00000060 0x50 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_aranges + 0x000000b0 0x30 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_aranges + 0x000000e0 0x80 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_aranges + 0x00000160 0x80 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_aranges + 0x000001e0 0x30 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_aranges + 0x00000210 0x78 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_aranges + 0x00000288 0x30 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_aranges + 0x000002b8 0x60 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_aranges + 0x00000318 0x28 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_aranges + 0x00000340 0x38 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_aranges + 0x00000378 0x58 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.debug_line 0x00000000 0x2a7b + .debug_line 0x00000000 0x199 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .debug_line 0x00000199 0x269 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .debug_line 0x00000402 0x1af build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .debug_line 0x000005b1 0x2a6 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_line 0x00000857 0x379 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_line 0x00000bd0 0xa79 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_line 0x00001649 0x331 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_line 0x0000197a 0x2d8 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_line 0x00001c52 0x273 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_line 0x00001ec5 0x223 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_line 0x000020e8 0x282 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_line 0x0000236a 0xdf ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_line 0x00002449 0x246 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_line 0x0000268f 0x3ec ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.debug_str 0x00000000 0x11854 + .debug_str 0x00000000 0x11854 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + 0x5bd (size before relaxing) + .debug_str 0x00011854 0x82b build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .debug_str 0x00011854 0x2bc build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .debug_str 0x00011854 0x5e51 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_str 0x00011854 0x5e69 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_str 0x00011854 0x87a5 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_str 0x00011854 0x7da9 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_str 0x00011854 0x789f ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_str 0x00011854 0x426e ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_str 0x00011854 0x84e9 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_str 0x00011854 0x6346 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_str 0x00011854 0x3e11 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_str 0x00011854 0x53e1 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_str 0x00011854 0x8227 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.comment 0x00000000 0x6c + .comment 0x00000000 0x6c build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + 0x47 (size before relaxing) + .comment 0x0000006c 0x47 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .comment 0x0000006c 0x47 build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .comment 0x0000006c 0x27 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.ARM.attributes + 0x00000000 0x32 + .ARM.attributes + 0x00000000 0x32 build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .ARM.attributes + 0x00000032 0x32 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .ARM.attributes + 0x00000064 0x32 build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .ARM.attributes + 0x00000096 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .ARM.attributes + 0x000000c8 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .ARM.attributes + 0x000000fa 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .ARM.attributes + 0x0000012c 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .ARM.attributes + 0x0000015e 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .ARM.attributes + 0x00000190 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .ARM.attributes + 0x000001c2 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .ARM.attributes + 0x000001f4 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .ARM.attributes + 0x00000226 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .ARM.attributes + 0x00000258 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .ARM.attributes + 0x0000028a 0x32 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .ARM.attributes + 0x000002bc 0x32 /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a(libc_a-memset.o) + +.debug_frame 0x00000000 0x74c + .debug_frame 0x00000000 0x2c build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + .debug_frame 0x0000002c 0x50 build/.objs/gpio/linux/arm32/release/user/src/main.c.o + .debug_frame 0x0000007c 0x7c build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + .debug_frame 0x000000f8 0x80 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_frame 0x00000178 0x70 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_frame 0x000001e8 0x11c ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_frame 0x00000304 0xe0 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_frame 0x000003e4 0x4c ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_frame 0x00000430 0xd8 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_frame 0x00000508 0x40 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_frame 0x00000548 0xa0 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_frame 0x000005e8 0x38 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_frame 0x00000620 0x50 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_frame 0x00000670 0xb0 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_frame 0x00000720 0x2c /home/time/doc/mybin/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a(libc_a-memset.o) + +.debug_loclists + 0x00000000 0x100c + .debug_loclists + 0x00000000 0x96 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_loclists + 0x00000096 0xf9 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_loclists + 0x0000018f 0x7ec ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_loclists + 0x0000097b 0x87 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_loclists + 0x00000a02 0xb6 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_loclists + 0x00000ab8 0xb4 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_loclists + 0x00000b6c 0x29 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_loclists + 0x00000b95 0x128 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_loclists + 0x00000cbd 0x80 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_loclists + 0x00000d3d 0x17 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_loclists + 0x00000d54 0x2b8 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.debug_rnglists + 0x00000000 0x325 + .debug_rnglists + 0x00000000 0x37 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_rnglists + 0x00000037 0x1f ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_rnglists + 0x00000056 0x109 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_rnglists + 0x0000015f 0x5b ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_rnglists + 0x000001ba 0x20 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_rnglists + 0x000001da 0x61 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_rnglists + 0x0000023b 0x1f ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_rnglists + 0x0000025a 0x43 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_rnglists + 0x0000029d 0x19 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_rnglists + 0x000002b6 0x25 ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_rnglists + 0x000002db 0x4a ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + +.debug_macro 0x00000000 0x4b2d + .debug_macro 0x00000000 0x88 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00000088 0xae4 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00000b6c 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00000b88 0x34e ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00000ed6 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00000ef8 0xe8 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00000fe0 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00001056 0x2ce ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00001324 0x76 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x0000139a 0x37e ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x00001718 0xca ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_all.o) + .debug_macro 0x000017e2 0x88 ../../libopencm3/lib/libopencm3_stm32h7.a(gpio_common_f0234.o) + .debug_macro 0x0000186a 0xdd ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00001947 0x189 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00001ad0 0x16 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00001ae6 0x1d4 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00001cba 0x7cc ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x00002486 0x1c ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x000024a2 0x143 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x000025e5 0x46 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc.o) + .debug_macro 0x0000262b 0x94 ../../libopencm3/lib/libopencm3_stm32h7.a(rcc_common_all.o) + .debug_macro 0x000026bf 0x8b ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x0000274a 0x452 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00002b9c 0x6e ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00002c0a 0x3b5 ../../libopencm3/lib/libopencm3_stm32h7.a(vector.o) + .debug_macro 0x00002fbf 0x49 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00003008 0x69 ../../libopencm3/lib/libopencm3_stm32h7.a(systick.o) + .debug_macro 0x00003071 0x123 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003194 0x29 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x000031bd 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x000031df 0x60 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x0000323f 0x5c ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x0000329b 0x3c ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x000032d7 0x34 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x0000330b 0x16 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003321 0x11c ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x0000343d 0x94 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x000034d1 0x57 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003528 0x38c ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x000038b4 0x16 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x000038ca 0x4a ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003914 0x34 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003948 0x10 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003958 0x52 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x000039aa 0x1de ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003b88 0x22 ../../libopencm3/lib/libopencm3_stm32h7.a(scb.o) + .debug_macro 0x00003baa 0x6a ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00003c14 0x68 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x00003c7c 0x458 ../../libopencm3/lib/libopencm3_stm32h7.a(nvic.o) + .debug_macro 0x000040d4 0x40 ../../libopencm3/lib/libopencm3_stm32h7.a(assert.o) + .debug_macro 0x00004114 0x8e ../../libopencm3/lib/libopencm3_stm32h7.a(flash_common_all.o) + .debug_macro 0x000041a2 0xaf ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00004251 0xa6 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x000042f7 0x7d2 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) + .debug_macro 0x00004ac9 0x64 ../../libopencm3/lib/libopencm3_stm32h7.a(pwr.o) diff --git a/1gpio/bin/gpio.srec b/1gpio/bin/gpio.srec new file mode 100755 index 0000000..676772d --- /dev/null +++ b/1gpio/bin/gpio.srec @@ -0,0 +1,217 @@ +S02B00002F686F6D652F74696D652F646F632F636F646566696C652F656D62652F426C6F672F73746D33322FBD +S3150800000000000220BD090008B9090008B709000860 +S31508000010B7090008B7090008B7090008000000007A +S31508000020000000000000000000000000B9090008F8 +S31508000030B909000800000000B9090008C904000849 +S31508000040B7090008B7090008B7090008B709000882 +S31508000050B7090008B7090008B7090008B709000872 +S31508000060B7090008B7090008B7090008B709000862 +S31508000070B7090008B7090008B7090008B709000852 +S31508000080B7090008B7090008B7090008B709000842 +S31508000090B7090008B7090008B7090008B709000832 +S315080000A0B7090008B7090008B7090008B709000822 +S315080000B0B7090008B7090008B7090008B709000812 +S315080000C0B7090008B7090008B7090008B709000802 +S315080000D0B7090008B7090008B7090008B7090008F2 +S315080000E0B7090008B7090008B7090008B7090008E2 +S315080000F0B7090008B7090008B7090008B7090008D2 +S31508000100B7090008B7090008B7090008B7090008C1 +S31508000110B7090008B7090008B7090008B7090008B1 +S31508000120B7090008B7090008B7090008B7090008A1 +S31508000130B7090008B7090008B7090008B709000891 +S31508000140B7090008B7090008B7090008B709000881 +S31508000150B7090008B7090008B7090008B709000871 +S31508000160B7090008B7090008B7090008B709000861 +S31508000170B7090008B7090008B7090008B709000851 +S31508000180B7090008B7090008B7090008B709000841 +S31508000190B7090008B7090008B7090008B709000831 +S315080001A0B7090008B7090008B7090008B709000821 +S315080001B0B7090008B7090008B7090008B709000811 +S315080001C0B7090008B7090008B7090008B709000801 +S315080001D0B7090008B7090008B7090008B7090008F1 +S315080001E0B7090008B7090008B7090008B7090008E1 +S315080001F0B7090008B7090008B7090008B7090008D1 +S31508000200B7090008B7090008B7090008B7090008C0 +S31508000210B7090008B7090008B7090008B7090008B0 +S31508000220B7090008B7090008B7090008B7090008A0 +S31508000230B7090008B7090008B7090008B709000890 +S31508000240B7090008B7090008B7090008B709000880 +S31508000250B7090008B7090008B7090008B709000870 +S31508000260B7090008B7090008B7090008B709000860 +S31508000270B7090008B7090008B7090008B709000850 +S31508000280B7090008B7090008B7090008B709000840 +S31508000290B7090008B709000880B500AF41F6044061 +S315080002A000F07CFB082300220121104800F02BF9FE +S315080002B00823002200210D4800F045F908210B48C3 +S315080002C000F012F90A4B1B68094A43F4807313605D +S315080002D041F6024000F062FB4FF40053022200216F +S315080002E0044800F010F900BF80BD00BF0010025896 +S315080002F0004802580008025880B500AF4FF4407015 +S3150800030000F0CFFB00F02CF84FF47A7000F0BCF840 +S31508000310FFF7C2FF4FF400510F4800F0E8F8034614 +S31508000320002BF7D0142000F095F84FF400510A4836 +S3150800033000F0DDF80346002B03D00821074800F03B +S31508000340D9F800BF4FF40051034800F0D0F803462F +S31508000350002BF7D1DEE700BF00080258001002584C +S3150800036080B58CB000AF3B462C220021184600F021 +S3150800037091FC41F6074000F011FB41F6816000F060 +S315080003800DFB022301220121304800F0BCF80223AC +S31508000390022200212D4800F0D6F80023FB6203E074 +S315080003A000BFFB6A0133FB62FB6A132BF8D90221F3 +S315080003B0264800F097F800233B7002237B70244BF5 +S315080003C07B6005233B72C0237B8102233B73022398 +S315080003D07B730223BB7320233B7481237B82022316 +S315080003E03B7502237B750223BB7520233B7681234D +S315080003F07B8302233B7702237B770223BB77002389 +S3150800040087F82030082387F82130042387F822301C +S31508000410042387F82330042387F82430042387F835 +S315080004202530042387F82630012387F8273002234E +S3150800043087F82830002387F829303B46184600F00D +S3150800044063F900BF3037BD4680BD00BF001C0258A7 +S3150800045040787D0180B485B000AF7860094B1B6891 +S31508000460FB6001E030BF00BF064B1A68FB68D31A71 +S315080004707A689A42F6D800BF00BF1437BD465DF8C1 +S31508000480047B70472400002080B582B000AF7860F6 +S31508000490042000F0E9FA002000F042FA02467B68E0 +S315080004A0B2FBF3F3013B184600F0D8FA00F0F4FA71 +S315080004B00F21FF2000F0FEFA00F0E0FA00F0E5FA5E +S315080004C000BF0837BD4680BD80B400AF044B1B682B +S315080004D00133034A136000BFBD465DF8047B7047CD +S315080004E02400002081617047090481617047006912 +S315080004F008407047436901EA030221EA030141EA19 +S315080005000241816170472DE9F04105680026C468FB +S315080005104FF0030E43FA06F7FF070DD577000EFADC +S3150800052007FC01FA07F802FA07F725EA0C0524EA98 +S315080005300C0448EA05053C430136102EEAD105604D +S31508000540C460BDE8F081012941680CBF194399438D +S31508000550F0B5416000248168032643FA04F5ED07E7 +S3150800056007D5650006FA05F702FA05F521EA070137 +S3150800057029430134102CF0D18160F0BD2DE9F043F8 +S3150800058091F800C0BCF1000F00F0A580012A26D022 +S31508000590574B9E1F022A18BF1E46013A554D002387 +S315080005A0B1F8028045F8323008F1FF3355F8324089 +S315080005B02343D4B245F83230A700B0FBFCF34E48CB +S315080005C0FFB2B3FBF0FCACF1030001284B4808D896 +S315080005D00423D0F82CE4BB404EEA03030DE0484E52 +S315080005E0DBE7ACF1050EBEF1030F76D80823D0F889 +S315080005F02C9403FA07FE4EEA0903C0F82C340CFBC8 +S3150800060008F3B3F5D27F09D8DFF8F0C00220DCF88A +S315080006102CE4B84040EA0E00CCF82C0467000879B0 +S3150800062004EB4404E4B2B0B155F832C000F1FF3E21 +S315080006304CEA4E2CDFF8C4E045F832C04FF4803C53 +S31508000640DEF82C840CFA04FCB3FBF0F04CEA080C38 +S31508000650CEF82CC430804879B0B155F832C000F1D4 +S31508000660FF3E4CEA0E4CDFF894E045F832C04FF4F2 +S31508000670003CDEF82C840CFA04FCB3FBF0F04CEAE0 +S31508000680080CCEF82CC47080897999B155F83200D7 +S3150800069001F1FF3C40EA0C6045F832004FF4802235 +S315080006A01648A240D0F82C54B3FBF1F32A43C0F8FD +S315080006B02C24B380114AFFB24FF08073D2F800148D +S315080006C0BB400B43C2F800344FF00073BB40D2F86E +S315080006D000141942FBD0BDE8F083DFF828E0734523 +S315080006E08DD94FF00C0ED0F82C340EFA07FE73E7AE +S315080006F01A0000203044025840420F0000400258B9 +S315080007000E0000203F548900F8B5814B0446D3F803 +S31508000710002442F00102C3F80024D3F8102422F082 +S315080007200702C3F81024D3F8102412F0380FFAD1B0 +S315080007300122C3F8002494F8291094F8280000F040 +S315080007402FFA94F8270000F057FA94F8260000F0DC +S31508000750D3F994F82630002B00F0C58000F0BCF9D8 +S3150800076063688BB16A4BD3F8002442F48032C3F82D +S315080007700024D3F800249203FBD563684FF47A72F9 +S31508000780B3FBF2F3634A1384237C227A1B03617852 +S3150800079043EA0213227E0B4343EA02535C4AC2F839 +S315080007A02834002900F0A2806568002304F10801B6 +S315080007B02846C2F82C340122FFF7E0FE022204F193 +S315080007C010012846FFF7DAFE2846032204F118012D +S315080007D0FFF7D4FE23784F48002B40F08980C38961 +S315080007E094F8245000264A4F94F8201094F82120B3 +S315080007F003800729C7F818644FEA0516D7F818C4FE +S3150800080046EA012646EA020646EA0C06C7F81864CE +S3150800081006D90B2994BF0739063943FA01F18BB279 +S31508000820072A438009D90B2A95BF073A911F43FA2D +S3150800083002F20B4194BF93B29BB2032D94F8231096 +S31508000840334E8CBFEA1E1A464FF00005838084BFDC +S3150800085043FA02F292B20329428194F82220C6F89A +S315080008601C544FEA01258CBF0339194645EA02157F +S31508000870D6F81C7488BF43FA01F145EA070588BF14 +S3150800088089B2032AC6F81C548CBF033A1A4601815A +S3150800089088BF43FA02F294F8251088BF92B203295A +S315080008A0C2801B4AD2F820444FF00004C2F8204404 +S315080008B0D2F8204444EA011484BF033943FA01F10B +S315080008C0C2F8204488BF8BB28381D2F8103443F033 +S315080008D00303C2F81034D2F810340D4AC3F3C20326 +S315080008E0032B0FD1F8BD00F0FFF839E70A4D5CE796 +S315080008F0012B09BF63684023084AB3FBF2F308BF1C +S315080009009BB26DE7D2F81034C3F3C203E8E700BF21 +S3150800091000400258000000200090D00340420F001B +S3150800092008B509282CD8DFE800F00A051C0A0D0DC1 +S3150800093010131619154B1888154B584308BD134B39 +S315080009405888F9E7114B9888F6E7104BD888F3E7EB +S315080009500E4B1889F0E70D4B5889EDE70B4B988934 +S31508000960EAE70C4BD3F84C3413F0405FC3F301723B +S3150800097008D0022A08D1054B188C4FF47A73DCE7A5 +S3150800098000F0A8F80448D9E70020D7E700000020BF +S3150800099040420F00004002580090D003430901224C +S315080009A000F01F0003F1B043824003F511331968C4 +S315080009B00A431A607047FEE77047000038B51D4ABB +S315080009C01D4B1E498B4220D31D4A0021934221D339 +S315080009D04FF0E0231B4C1C4DD3F8142D42F4007243 +S315080009E0C3F8142DD3F8882D42F47002C3F8882D65 +S315080009F0AC4212D3154C164DAC4212D3154CFFF728 +S31508000A007BFC154DAC4210D338BD52F8040B43F8A5 +S31508000A10040BD7E743F8041BD8E754F8043B984778 +S31508000A20E6E754F8043B9847E6E754F8043B98474A +S31508000A30E8E700BF380D0008000000202400002069 +S31508000A4028000020380D0008380D0008380D000869 +S31508000A50380D0008380D0008380D000820F07F40D2 +S31508000A604FF0E023586170474FF0E02200F0040091 +S31508000A70136923F004030343136170474FF0E02220 +S31508000A80136943F00203136170474FF0E0221369BC +S31508000A9043F00103136170474FF0E02300229A6187 +S31508000AA0704740F0BF604FF0E02340F40030C3F8D1 +S31508000AB00C0D7047952804D900F00F00044BC1545B +S31508000AC0704700F1604000F564400170704700BF50 +S31508000AD014ED00E0FEE70000024A136843F4807351 +S31508000AE01360704700200052024A136823F480738B +S31508000AF01360704700200052034A136823F00F035F +S31508000B0003431360704700BF00200052044AD2F81E +S31508000B100C3823F0070343F00203C2F80C38704779 +S31508000B2000400258044AD2F80C3823F0070343F071 +S31508000B300603C2F80C3870470040025808B50B0186 +S31508000B4070B943F0040309485242D0F80C1802F071 +S31508000B50020221F03F010A431A43C0F80C2808BDD7 +S31508000B6009B9FFF7B7FF43F00C03ECE7004002585A +S31508000B70044AD2F80C3823F0070343F00103C2F8FD +S31508000B800C38704700400258044AD2F80C3823F053 +S31508000B90070343F00503C2F80C38704700400258B3 +S31508000BA008B5072807D8DFE800F0040C0F12121D55 +S31508000BB01D21FFF7B7FF0F4AD2F804389B04FBD56F +S31508000BC008BDFFF7E1FFF6E7FFF7A0FFF3E7A0F19F +S31508000BD0040C0021DCF1000242EB0C020020FFF7B6 +S31508000BE0ADFFE8E7053842424241F7E7FFF7C0FFA5 +S31508000BF0E1E700BF00400258F8B5074608B9FFF715 +S31508000C0069FF204B421E204E1B68C3F30B03B3F546 +S31508000C10906F0FD1D6F818381C4923F440438A5CE4 +S31508000C2043EA8233C6F81838174AD2F818389B04AC +S31508000C30FBD5F8BD1649B3F58A6FD6F818588C5CFB +S31508000C4025F440454FEA843418D141F68160FFF710 +S31508000C50A5FE012F4FF0B0430AD145F44045C6F82A +S31508000C601858D3F82C2442F00102C3F82C24DBE7E9 +S31508000C70D3F82C2422F00102C3F82C242C43C6F8FE +S31508000C801848D1E70010005C00400258340D0008EF +S31508000C90300D0008830730B546D08418844604E032 +S31508000CA003F8011B9D0704D09C46A4456346F7D16B +S31508000CB030BD013A0244A2EB0C02032A29D9CCB270 +S31508000CC004EB04240F2A04EB04442FD9A2F1100CD8 +S31508000CD02CF00F0C03F11005AC44C3E90044C3E93A +S31508000CE0024410336345F8D112F00C0F02F00F0ED0 +S31508000CF018D02EF0030C9C44AEF104051A4642F8AF +S31508000D00044B6245FBD125F0030404330EF00302BD +S31508000D102344002ACCD0C9B21A4403F8011B9342D3 +S31508000D20FBD130BD7246F4E70346C6E79646E0E7D0 +S30D08000D300003020103020100A1 +S31508000D3840004000400040004000400040000000DD +S31508000D48000000000000000000000000000000008D +S30908000D580000000089 +S705080009BD2C diff --git a/1gpio/cortex-m-generic.ld b/1gpio/cortex-m-generic.ld new file mode 100644 index 0000000..b942c23 --- /dev/null +++ b/1gpio/cortex-m-generic.ld @@ -0,0 +1,117 @@ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 0x200000 /* Flash 2MB */ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000 /* 128 KB */ + ram2 (rwx) : ORIGIN = 0x24000000, LENGTH = 0x80000 /* 512 KB */ +} + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + } >rom + + /* C++ Static constructors/destructors, also used for __attribute__ + * ((constructor)) and the likes */ + .preinit_array : { + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + } >rom + .init_array : { + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + } >rom + .fini_array : { + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + } >rom + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom + + . = ALIGN(4); + _etext = .; + + /* ram, but not cleared on reset, eg boot/app comms */ + .noinit (NOLOAD) : { + *(.noinit*) + } >ram + . = ALIGN(4); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + *(.ramtext*) /* "text" functions to run in ram */ + . = ALIGN(4); + _edata = .; + } >ram AT >rom + _data_loadaddr = LOADADDR(.data); + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + /* Heap 分配到第二块 RAM */ + .heap : { + _sheap = .; + . = ORIGIN(ram2) + LENGTH(ram2); + _eheap = .; + } >ram2 + + /* 第二块 RAM,用于大数组或 heap */ + /* + .ext_ram (NOLOAD) : { + _sext_ram = .; + *(.ext_ram*) + *(.bss_ext_ram*) + . = ALIGN(4); + _eext_ram = .; + } > ram2 + */ + + . = ALIGN(4); + end = .; +} + +PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); + +PROVIDE(_sheap = ORIGIN(ram2)); +PROVIDE(_eheap = ORIGIN(ram2) + LENGTH(ram2)); diff --git a/1gpio/makefile b/1gpio/makefile new file mode 100644 index 0000000..e236087 --- /dev/null +++ b/1gpio/makefile @@ -0,0 +1,68 @@ +# this is the build file for project stm32h7 +# it is autogenerated by the xmake build system. +# do not edit by hand. + +ifneq ($(VERBOSE),1) +VV=@ +endif + +CXX=/usr/bin/g++ +CU=/usr/bin/clang +MM=/usr/bin/gcc +GC=/usr/local/go/bin/go +AS=/usr/bin/gcc +CC=/usr/bin/gcc +RC=/home/time/.cargo/bin/rustc +MXX=/usr/bin/g++ + +LD=/usr/bin/g++ +RCLD=/home/time/.cargo/bin/rustc +GCLD=/usr/local/go/bin/go +SH=/usr/bin/g++ +RCSH=/home/time/.cargo/bin/rustc +AR=/usr/bin/ar +RCAR=/home/time/.cargo/bin/rustc +GCAR=/usr/local/go/bin/go + +gpio_LD=/home/time/doc/mybin/arm-none-eabi/bin/arm-none-eabi-g++ +gpio_CC=/home/time/doc/mybin/arm-none-eabi/bin/arm-none-eabi-gcc + +gpio_CCFLAGS=-g -O0 -Iuser/inc -I../../libopencm3/include -DSTM32H7 -mthumb -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard +gpio_LDFLAGS=-L../../libopencm3/lib -lopencm3_stm32h7 -lc -lgcc -lnosys -mthumb -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -T./cortex-m-generic.ld --static -nostartfiles -Wl,--gc-sections -Wl,-Map=/home/time/doc/codefile/embe/Blog/stm32/stm32h7/1gpio_xmake/bin/gpio.map + +default: gpio + +all: gpio + +.PHONY: default all gpio + +gpio: bin/gpio.elf +bin/gpio.elf: build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o build/.objs/gpio/linux/arm32/release/user/src/main.c.o build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + @echo linking.release gpio.elf + @mkdir -p bin + $(VV)$(gpio_LD) -o bin/gpio.elf build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o build/.objs/gpio/linux/arm32/release/user/src/main.c.o build/.objs/gpio/linux/arm32/release/user/src/systick.c.o $(gpio_LDFLAGS) + +build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o: user/src/gpio.c + @echo compiling.release user/src/gpio.c + @mkdir -p build/.objs/gpio/linux/arm32/release/user/src + $(VV)$(gpio_CC) -c $(gpio_CCFLAGS) -o build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o user/src/gpio.c + +build/.objs/gpio/linux/arm32/release/user/src/main.c.o: user/src/main.c + @echo compiling.release user/src/main.c + @mkdir -p build/.objs/gpio/linux/arm32/release/user/src + $(VV)$(gpio_CC) -c $(gpio_CCFLAGS) -o build/.objs/gpio/linux/arm32/release/user/src/main.c.o user/src/main.c + +build/.objs/gpio/linux/arm32/release/user/src/systick.c.o: user/src/systick.c + @echo compiling.release user/src/systick.c + @mkdir -p build/.objs/gpio/linux/arm32/release/user/src + $(VV)$(gpio_CC) -c $(gpio_CCFLAGS) -o build/.objs/gpio/linux/arm32/release/user/src/systick.c.o user/src/systick.c + +clean: clean_gpio + +clean_gpio: + @rm -rf bin/gpio.elf + @rm -rf bin/gpio.sym + @rm -rf build/.objs/gpio/linux/arm32/release/user/src/gpio.c.o + @rm -rf build/.objs/gpio/linux/arm32/release/user/src/main.c.o + @rm -rf build/.objs/gpio/linux/arm32/release/user/src/systick.c.o + diff --git a/1gpio/user/inc/gpio.h b/1gpio/user/inc/gpio.h new file mode 100644 index 0000000..d5e805e --- /dev/null +++ b/1gpio/user/inc/gpio.h @@ -0,0 +1,8 @@ +#ifndef _GPIO_H +#define _GPIO_H + +#include "main.h" + +void user_gpio_setup(void); + +#endif diff --git a/1gpio/user/inc/main.h b/1gpio/user/inc/main.h new file mode 100644 index 0000000..630ef02 --- /dev/null +++ b/1gpio/user/inc/main.h @@ -0,0 +1,17 @@ +#ifndef _MAIN_H +#define _MAIN_H + +#include + +// 包含libopencm3内核的相关头文件 +#include // 系统滴答定时器相关定义 +#include // 系统控制块相关定义 + +// 包含STM32 H系列微控制器的相关头文件 +#include // 复位和时钟控制相关定义 +#include // 电源控制相关定义 +#include // 通用输入输出相关定义 +#include // 闪存控制相关定义 +#include // 中断向量控制器相关定义 + +#endif diff --git a/1gpio/user/inc/systick.h b/1gpio/user/inc/systick.h new file mode 100644 index 0000000..cc59ea0 --- /dev/null +++ b/1gpio/user/inc/systick.h @@ -0,0 +1,11 @@ +#ifndef _SYSTICK_H +#define _SYSTICK_H + +#include "main.h" + +extern volatile uint32_t systick; + +void user_delay_ms(uint32_t ms); +void systick_init(uint32_t ticks); + +#endif diff --git a/1gpio/user/src/gpio.c b/1gpio/user/src/gpio.c new file mode 100644 index 0000000..02c9b77 --- /dev/null +++ b/1gpio/user/src/gpio.c @@ -0,0 +1,47 @@ +#include "gpio.h" + +/** + * @brief 初始化用户GPIO引脚配置 + * + * @details 该函数用于初始化和配置用户所需的GPIO引脚,主要包括以下配置： + * 1. 使能GPIOE时钟,配置PE3引脚为推挽输出模式,速度为2MHz,初始状态为低电平 + * 2. 使能备份区域寄存器访问（通过设置PWR_CR1_DBP位） + * 3. 使能GPIOC时钟,配置PC13引脚为输入模式,并启用下拉电阻 + * 这些配置通常用于设置LED控制引脚和按钮输入引脚等常见外设接口。 + * + * @note 该函数应在系统初始化阶段调用,确保GPIO引脚在使用前已正确配置。 + * PE3引脚配置为输出模式,可用于驱动LED或其他输出设备。 + * PC13引脚配置为输入模式并启用下拉电阻,适合连接按钮或开关等输入设备。 + * PWR_CR1_DBP位的设置允许访问备份寄存器,这在某些应用中可能是必要的。 + * + * @warning 在调用此函数前,应确保系统时钟已经正确配置。 + * 修改GPIO配置可能会影响连接到这些引脚的外设功能。 + * 在多任务系统中,如果多个任务访问同一GPIO,可能需要添加同步机制。 + * + * @see rcc_periph_clock_enable(), gpio_mode_setup(), gpio_set_output_options(), gpio_clear() + */ +void user_gpio_setup(void) +{ + // 使能GPIOE端口的时钟,必须先使能时钟才能配置和使用该端口的引脚 + rcc_periph_clock_enable(RCC_GPIOE); + + // 配置GPIOE端口的引脚3为输出模式,不使用上拉或下拉电阻 + gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3); + + // 设置GPIOE端口引脚3的输出选项：推挽输出类型,速度为2MHz + gpio_set_output_options(GPIOE, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, GPIO3); + + // 将GPIOE端口引脚3设置为低电平,也就是灯灭 + gpio_clear(GPIOE, GPIO3); + + // 使能备份域访问,通过设置电源控制寄存器1的DBP位 + // 这是访问RTC、备份寄存器等备份域外设的必要步骤 + // PC13-PC15是备份域的GPIO引脚,需要使能备份域访问才能配置这些引脚 + PWR_CR1 |= PWR_CR1_DBP; + + // 使能GPIOC端口的时钟,必须先使能时钟才能配置和使用该端口的引脚 + rcc_periph_clock_enable(RCC_GPIOC); + + // 配置GPIOC端口的引脚13为输入模式,并启用下拉电阻 + gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO13); +} diff --git a/1gpio/user/src/main.c b/1gpio/user/src/main.c new file mode 100644 index 0000000..1bc1f39 --- /dev/null +++ b/1gpio/user/src/main.c @@ -0,0 +1,174 @@ +#include "main.h" +#include "gpio.h" +#include "systick.h" + +static void system_clock_setup(void); + +/** + * @brief 主函数,程序入口点 + * + * @details 该函数是程序的入口点,负责系统的初始化和主循环。主要执行以下步骤： + * 1. 设置中断优先级分组为16个优先级,无子优先级 + * 2. 初始化系统时钟配置 + * 3. 初始化SysTick定时器,设置为每毫秒产生一次中断 + * 4. 初始化用户GPIO引脚配置 + * 5. 进入主循环,检测按钮状态并控制LED + * 主循环中检测PC13引脚（按钮）的状态,当检测到按钮按下时, + * 进行消抖处理,然后切换PE3引脚（LED）的状态,并等待按钮释放。 + * + * @note 该函数不会返回,除非发生严重错误。 + * 主循环中的按钮检测包含了简单的消抖处理,通过延时和再次检测实现。 + * 程序使用了轮询方式检测按钮状态,适用于简单的嵌入式应用。 + * + * @warning 在修改此函数时,应确保系统初始化顺序正确,特别是时钟配置。 + * 按钮消抖延时时间(20ms)可能需要根据实际硬件特性进行调整。 + * 如果使用RTOS,此函数结构需要重新设计以适应任务调度。 + * + * @see scb_set_priority_grouping(), system_clock_setup(), systick_init(), + * user_gpio_setup(), user_delay_ms(), gpio_get(), gpio_toggle() + */ +int main(void) +{ + // 设置中断优先级分组为16个主优先级,无子优先级 + // 这意味着每个中断都有独立的优先级,没有子优先级用于同一优先级中断的排序 + scb_set_priority_grouping(SCB_AIRCR_PRIGROUP_GROUP16_NOSUB); + + // 初始化系统时钟配置 + system_clock_setup(); + + // 初始化SysTick定时器,参数1000U表示每秒产生1000次中断,即每1ms一次 + systick_init(1000U); + + // 初始化用户GPIO引脚配置 + // 根据gpio的代码,这包括配置PE3为输出（LED）和PC13为输入（按钮） + user_gpio_setup(); + + // 主循环,程序将在此无限循环 + while (1) + { + // 检测PC13引脚（按钮）的状态,如果为高电平（按钮按下）则执行以下代码 + if(gpio_get(GPIOC, GPIO13)) + { + // 延时20ms,用于按钮消抖 + // 按钮在按下和释放时会产生机械抖动,延时可以避免误检测 + user_delay_ms(20); + + // 再次检测按钮状态,确认按钮确实被按下（不是抖动） + if(gpio_get(GPIOC, GPIO13)) + { + // 切换PE3引脚（LED）的状态 + // 如果LED当前是亮的状态,则熄灭；如果是灭的状态,则点亮 + gpio_toggle(GPIOE, GPIO3); + } + + // 等待按钮释放 + // 这是一个空循环,一直检测直到按钮被释放（PC13变为低电平） + // 这样可以防止在按钮按住期间多次触发LED切换 + while(gpio_get(GPIOC, GPIO13)); + } + } + + // 理论上不会执行到这里,因为上面是无限循环 + // 这行代码主要是为了满足C语言标准中main函数应有返回值的要求 + return 0; +} + +/** + * @brief 系统时钟配置函数 + * + * @details 该函数用于初始化和配置系统的时钟树,包括PLL锁相环、系统时钟分频、Flash等待状态 + * 和电源管理设置。函数执行以下主要步骤： + * 1. 初始化GPIOH和SYSCFG时钟,配置GPIOH1引脚为输出模式 + * 2. 设置PLL配置结构体的各个参数,包括时钟源选择、PLL分频系数等 + * 3. 配置系统时钟分频参数,确定各个总线的时钟频率 + * 4. 设置Flash等待状态,确保Flash访问速度与系统时钟频率匹配 + * 5. 配置电压缩放比例和电源模式 + * 6. 应用PLL配置,完成系统时钟设置 + * 这些配置参数与STM32CubeMX工具生成的配置可以一一对应,便于调试和验证。 + * + * @note 该函数应在系统启动初期调用,确保系统时钟正确配置后再进行其他初始化。 + * 函数中配置的GPIOH1引脚可能用于指示时钟配置状态或调试目的。 + * PLL配置基于25MHz的外部高速晶振(HSE),通过PLL1产生系统时钟。 + * PLL2和PLL3可用于为特定外设提供时钟。 + * 系统时钟配置完成后,CPU将运行在较高频率(约480MHz),具体取决于PLL1配置。 + * + * @warning 修改此函数中的时钟配置参数时,应确保不超过芯片的最大工作频率限制。 + * 不正确的时钟配置可能导致系统不稳定或无法正常工作。 + * 修改时钟配置可能会影响依赖于精确时序的外设(如UART、SPI等)。 + * 在多任务系统中,修改系统时钟可能需要重新调整定时器和调度器的配置。 + * + * @see rcc_periph_clock_enable(), gpio_mode_setup(), gpio_set_output_options(), + * gpio_set(), rcc_clock_setup_pll() + */ +static void system_clock_setup(void) +{ + // 初始化PLL配置结构体,所有成员清零 + struct rcc_pll_config pll_config = {0}; + + // 使能GPIOH端口时钟,用于配置GPIOH1引脚 + // OSC_IN是GPIOH0,OSC_OUT是GPIOH1 + rcc_periph_clock_enable(RCC_GPIOH); + // 使能SYSCFG时钟,用于系统配置 + rcc_periph_clock_enable(RCC_SYSCFG); + + // 配置GPIOH1引脚为输出模式,启用上拉电阻 + gpio_mode_setup(GPIOH, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO1); + // 设置GPIOH1引脚为推挽输出,速度为50MHz + gpio_set_output_options(GPIOH, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO1); + + // 短暂延时,确保GPIO配置稳定 + for (unsigned i = 0; i < 20; i++) + { + __asm__("nop"); // 空操作指令,用于延时 + } + // 将GPIOH1引脚设置为高电平 + gpio_set(GPIOH, GPIO1); + + // 设置系统时钟源为PLL + pll_config.sysclock_source = RCC_PLL; + // 设置PLL时钟源为外部高速晶振(HSE) + pll_config.pll_source = RCC_PLLCKSELR_PLLSRC_HSE; + // 设置HSE频率为25MHz + pll_config.hse_frequency = 25000000U; + + // 配置PLL1参数,这一部分可以和CubeMX进行一一对应 + // 系统时钟频率 = HSE / M * N / P = 25MHz / 5 * 192 / 2 = 480MHz + pll_config.pll1.divm = 5; + pll_config.pll1.divn = 192; + pll_config.pll1.divp = 2; + pll_config.pll1.divq = 2; + pll_config.pll1.divr = 2; + + // 配置PLL2参数 + pll_config.pll2.divm = 32; + pll_config.pll2.divn = 129; + pll_config.pll2.divp = 2; + pll_config.pll2.divq = 2; + pll_config.pll2.divr = 2; + + // 配置PLL3参数 + pll_config.pll3.divm = 32; + pll_config.pll3.divn = 129; + pll_config.pll3.divp = 2; + pll_config.pll3.divq = 2; + pll_config.pll3.divr = 2; + + // 配置系统时钟分频参数,还是可以和CubeMX进行一一对应 + pll_config.core_pre = RCC_D1CFGR_D1CPRE_BYP; // CPU核心时钟不分频 + pll_config.hpre = RCC_D1CFGR_D1HPRE_DIV2; // AHB总线时钟2分频 + pll_config.ppre1 = RCC_D2CFGR_D2PPRE_DIV2; // APB1总线时钟2分频 + pll_config.ppre2 = RCC_D2CFGR_D2PPRE_DIV2; // APB2总线时钟2分频 + pll_config.ppre3 = RCC_D1CFGR_D1PPRE_DIV2; // APB3总线时钟2分频 + pll_config.ppre4 = RCC_D3CFGR_D3PPRE_DIV2; // APB4总线时钟2分频 + + // 设置Flash等待状态为4个周期,确保在480MHz系统时钟下能正确访问Flash + pll_config.flash_waitstates = FLASH_ACR_LATENCY_4WS; + + // 配置电压缩放和电源模式 + pll_config.voltage_scale = PWR_VOS_SCALE_0; // 电压缩放级别0,最高性能模式 + pll_config.power_mode = PWR_SYS_LDO; // 使用LDO(低压差线性稳压器)电源模式 + pll_config.smps_level = 0; // SMPS(开关模式电源)级别 + + // 应用PLL配置,完成系统时钟设置 + rcc_clock_setup_pll(&pll_config); +} diff --git a/1gpio/user/src/systick.c b/1gpio/user/src/systick.c new file mode 100644 index 0000000..4b929cf --- /dev/null +++ b/1gpio/user/src/systick.c @@ -0,0 +1,145 @@ +#include "systick.h" + +/** + * @brief 系统毫秒计数器 + * + * @details 这是一个全局变量,用于记录系统运行的毫秒数。 + * 该变量在SysTick定时器中断服务程序(sys_tick_handler)中递增, + * 通常用于实现系统计时和延时功能（如user_delay_ms函数）。 + * 变量被声明为volatile,确保编译器不会优化掉对它的访问, + * 因为它可以在中断上下文中被修改,而主程序可能需要读取它的值。 + * + * @note 该变量的初始值为0,表示系统启动后经过的毫秒数。 + * 变量的递增频率取决于SysTick定时器的配置,通常为每毫秒递增一次。 + * 在32位系统上,该变量约每49.7天会溢出一次（从2^32-1回到0）。 + * + * @warning 在多任务或多线程环境中访问此变量时,可能需要添加适当的同步机制, + * 如禁用中断或使用原子操作,以避免竞态条件。 + * 不应直接修改此变量的值,除非有特殊需求并了解其影响。 + * + * @see sys_tick_handler(), user_delay_ms(), systick_init() + */ +volatile uint32_t systick = 0; + +/** + * @brief 执行WFI(Wait For Interrupt)指令,使处理器进入低功耗状态 + * + * @details 该函数使用内联汇编执行ARM Cortex-M处理器的WFI指令。 + * WFI指令会使处理器进入低功耗状态,直到下一个中断发生时才会唤醒处理器。 + * 该函数被声明为静态内联(always_inline),确保总是被内联展开以减少函数调用开销。 + * 使用volatile关键字防止编译器优化掉看似"无用"的指令。 + * + * @note 该函数不会改变处理器状态,只是暂停执行直到中断发生。 + * 在中断发生时,处理器会恢复执行WFI指令之后的代码。 + * 该函数通常用于在等待事件或延时期间降低系统功耗。 + * + * @warning 使用该函数时,确保系统中存在能够唤醒处理器的中断源, + * 否则处理器可能会一直保持低功耗状态。 + */ +static inline __attribute__((always_inline)) void __WFI(void) +{ + __asm volatile("wfi"); +} + +/** + * @brief 实现毫秒级延时的函数 + * + * @details 该函数使用SysTick定时器实现精确的毫秒级延时。函数记录当前的SysTick值作为起始时间, + * 然后进入循环等待,直到经过的时间达到指定的毫秒数。在等待期间,CPU会通过WFI指令 + * 进入低功耗状态,以降低系统功耗。该函数适用于裸机系统中的简单延时需求。 + * + * @param ms 要延时的毫秒数,取值范围为1到(2^32-1)毫秒。 + * + * @note 该函数是阻塞式的,在延时期间CPU无法执行其他任务。 + * 函数依赖于全局变量systick的正确更新,通常systick在SysTick中断服务程序中递增。 + * SysTick定时器应配置为每毫秒产生一次中断。 + * 函数内部使用了WFI指令降低功耗,但实际延时的精度取决于中断的频率和响应时间。 + * + * @warning 如果系统中没有中断或中断被禁用,使用此函数可能导致系统死锁。 + * 在实时性要求高的系统中,应谨慎使用阻塞式延时函数。 + * 最大延时时间受限于32位无符号整数的最大值(约49.7天)。 + * + * @see systick, __WFI() + */ +void user_delay_ms(uint32_t ms) +{ + // 记录开始延时的时刻（systick的当前值） + uint32_t start = systick; + + // 循环等待,直到经过的时间达到指定的毫秒数 + while (systick - start < ms) + { + // 进入低功耗模式,等待中断唤醒,有助于在延时时降低CPU功耗 + __WFI(); + } +} + +/** + * @brief 初始化SysTick定时器 + * + * @details 该函数用于初始化和配置ARM Cortex-M的SysTick定时器,使其能够以指定的频率产生中断。 + * 函数执行以下配置步骤： + * 1. 设置SysTick时钟源为AHB总线时钟 + * 2. 根据指定的中断频率计算并设置重载值 + * 3. 清除当前计数值 + * 4. 设置中断优先级 + * 5. 使能中断和计数器 + * 配置完成后,SysTick定时器将开始工作,并在每次计数到0时产生中断。 + * + * @param ticks 指定SysTick定时器的中断频率,单位为Hz（每秒中断次数） + * 例如,传入1000表示定时器每1秒产生1000次中断,即每1毫秒产生一次中断。 + * + * @note 该函数依赖于rcc_get_bus_clk_freq()函数获取CPU时钟频率。 + * SysTick中断优先级被设置为15（最低优先级）,在需要更高实时性的应用中可能需要调整。 + * 函数使用了库函数封装的方式操作SysTick寄存器,而不是直接寄存器访问。 + * 重载值的计算方式为：(CPU时钟频率 / ticks) - 1,确保ticks值不能导致计算结果超过24位最大值(16,777,215)。 + * + * @warning 如果ticks参数过大,可能导致重载值小于1,此时定时器可能无法正常工作。 + * 在调用此函数前,应确保CPU时钟已经正确配置。 + * 此函数会覆盖任何之前的SysTick配置,包括中断处理函数的注册。 + * + * @see sys_tick_handler(), systick, user_delay_ms() + */ +void systick_init(uint32_t ticks) +{ + // 设置SysTick时钟源为AHB总线时钟 + systick_set_clocksource(STK_CSR_CLKSOURCE_AHB); + + // 计算重载值：总线频率除以定时器周期数减1 + systick_set_reload((rcc_get_bus_clk_freq(RCC_CPUCLK) / ticks) - 1UL); + + // 清除SysTick当前值寄存器（被注释掉的代码） + //STK_CVR = 0UL; + // 使用函数方式清除SysTick计数器 + systick_clear(); + + // 设置SysTick中断优先级为15（最低优先级） + nvic_set_priority(NVIC_SYSTICK_IRQ, 15); + + // 使用函数方式配置SysTick控制寄存器（被注释掉的代码） + // STK_CSR = STK_CSR_CLKSOURCE | STK_CSR_TICKINT | STK_CSR_ENABLE; + // 分别使能SysTick中断和计数器 + systick_interrupt_enable(); + systick_counter_enable(); +} + +/** + * @brief SysTick定时器中断服务函数 + * + * @details 该函数是SysTick定时器的中断服务程序(ISR),每当SysTick定时器计数到0时触发。 + * 函数的主要功能是递增全局变量systick,该变量通常用于系统计时和延时功能。 + * + * @note 该函数应保持简短高效,因为它是中断服务程序,执行时间过长可能影响系统实时性。 + * systick变量通常定义为全局变量,用于记录系统运行的毫秒数（假设SysTick配置为1ms中断一次）。 + * 在多任务系统中,此函数可能需要添加任务切换相关的代码。 + * + * @warning 此函数不应被用户代码直接调用,它是由硬件自动调用的中断服务程序。 + * 在函数内部应避免调用可能导致长时间阻塞的函数或复杂的计算。 + * 如果systick变量在多线程/多任务环境中被访问,可能需要添加适当的同步机制。 + * + * @see systick, systick_init(), user_delay_ms() + */ +void sys_tick_handler(void) +{ + systick++; +} diff --git a/1gpio/xmake.lua b/1gpio/xmake.lua new file mode 100644 index 0000000..9b0a4ae --- /dev/null +++ b/1gpio/xmake.lua @@ -0,0 +1,101 @@ +-- 工程名 +set_project("stm32h7") + +-- 定义工具链 +toolchain("arm-none-eabi") + set_kind("standalone") + set_sdkdir("/home/time/doc/mybin/arm-none-eabi") +toolchain_end() + +-- 使用自定义的 arm-none-eabi 工具链 +set_toolchains("arm-none-eabi") + +-- 设置平台与架构 +set_plat("linux") +set_arch("arm32") + +-- 编译优化与调试 +set_optimize("none") +set_symbols("debug") + +-- 目标程序 +target("gpio") + -- 设置目标类型,编译为可执行文件 + set_kind("binary") + -- 添加源文件 + add_files("user/src/*.c") + -- 设置头文件路径 + add_includedirs("user/inc", {public = true}) + -- 设置输出目录 + set_targetdir("$(projectdir)/bin") + + -- 让 elf 文件名跟随 target 名 + on_load(function (target) + target:set("filename", target:name() .. ".elf") + -- 同时设置 map 文件输出到 bin + target:add("ldflags", + "-Wl,-Map=" .. path.join(target:targetdir(), target:name() .. ".map"), + {force = true} + ) + end) + + -- 架构 & FPU + add_cxflags("-mthumb", "-mcpu=cortex-m7", "-mfpu=fpv5-d16", "-mfloat-abi=hard", {force = true}) + add_asflags("-mthumb", "-mcpu=cortex-m7", "-mfpu=fpv5-d16", "-mfloat-abi=hard", {force = true}) + add_ldflags("-mthumb", "-mcpu=cortex-m7", "-mfpu=fpv5-d16", "-mfloat-abi=hard", {force = true}) + + -- 头文件路径 (libopencm3) + add_includedirs("../../libopencm3/include", {public = true}) + + -- 链接 libopencm3 + add_linkdirs("../../libopencm3/lib") + add_links("opencm3_stm32h7") + + -- 额外链接选项 + add_ldflags("-T./cortex-m-generic.ld", "--static", "-nostartfiles", "-Wl,--gc-sections", {force = true}) + add_syslinks("c", "gcc", "nosys") + + -- 预处理宏 + add_defines("STM32H7") + + -- 生成额外的二进制文件 + after_build(function (target) + local elf = target:targetfile() + local bindir = target:targetdir() + local name = target:name() + os.execv("arm-none-eabi-objcopy", {"-Obinary", elf, path.join(bindir, name .. ".bin")}) + os.execv("arm-none-eabi-objcopy", {"-Oihex", elf, path.join(bindir, name .. ".hex")}) + os.execv("arm-none-eabi-objcopy", {"-Osrec", elf, path.join(bindir, name .. ".srec")}) + os.execv("arm-none-eabi-objdump", {"-S", elf}, {stdout = path.join(bindir, name .. ".list")}) + end) + + -- 自定义清理逻辑 + on_clean(function (target) + os.rm("build") + os.rm("bin") + end) + +-- 定义 flash 任务（使用 openocd） +task("flash") + set_menu { + usage = "xmake flash [options]", + description = "Flash firmware to STM32H7 using OpenOCD.", + options = { + {'t', "target", "kv", nil, "Set the target name"} + } + } + on_run(function (args) + import("core.project.project") + + local tname = args.target or (project.targets()[1] and project.targets()[1]:name()) + assert(tname, "No target found!") + local t = project.target(tname) + assert(t, "Target " .. tname .. " not found!") + + local elf = t:targetfile() + os.execv("openocd", { + "-f", "interface/stlink.cfg", + "-f", "target/stm32h7x.cfg", + "-c", "program " .. elf .. " verify reset exit" + }) + end)