fe52fcdb1a
FLASH_BASE was already defined for some and PERIPH_BASE for all but one, but this makes these available for all families. Note that the value is identical for all familes (I doublechecked the more exotic ones such STM32H7), but it is still useful to have these defines to make code more readable and so that libopencm3 users can write portable code without having to check that these are identical on all STM32 families.
141 lines
5.6 KiB
C
141 lines
5.6 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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#define FLASH_BASE (0x08000000U)
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#define PERIPH_BASE (0x40000000U)
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#define INFO_BASE (0x1fff0000U)
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#define PERIPH_BASE_APB1 (0x40000000U)
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#define PERIPH_BASE_APB2 (0x40010000U)
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#define PERIPH_BASE_AHB1 (0x40020000U)
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#define PERIPH_BASE_IOPORT (0x48000000U)
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#define PERIPH_BASE_AHB2 (0x50000000U)
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#define FMC1_BANK_BASE (0x60000000U)
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#define FMC3_BANK_BASE (0x80000000U)
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#define QUADSPI_BANK_BASE (0x90000000U)
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
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#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
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#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
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#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
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#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
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#define CRS_BASE (PERIPH_BASE_APB1 + 0x2000)
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#define TAMP_BASE (PERIPH_BASE_APB1 + 0x2400)
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#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
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#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
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#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
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#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
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#define UART4_BASE (PERIPH_BASE_APB1 + 0x4C00)
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#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
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#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define FDCAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
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#define FDCAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
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#define FDCAN3_BASE (PERIPH_BASE_APB1 + 0x6c00)
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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#define I2C3_BASE (PERIPH_BASE_APB1 + 0x7800)
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#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)
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#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)
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#define I2C4_BASE (PERIPH_BASE_APB1 + 0x8400)
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#define UCPD1_BASE (PERIPH_BASE_APB1 + 0xA000)
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#define FDCAN1_RAM_BASE (PERIPH_BASE_APB1 + 0xA400)
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#define FDCAN2_RAM_BASE (PERIPH_BASE_APB1 + 0xA800)
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#define FDCAN3_RAM_BASE (PERIPH_BASE_APB1 + 0xAc00)
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/* APB2 */
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#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)
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#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200)
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#define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0300)
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#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
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#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
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#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3c00)
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#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)
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#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)
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#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)
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#define TIM20_BASE (PERIPH_BASE_APB2 + 0x5000)
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#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)
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#define HRTIM_BASE (PERIPH_BASE_APB2 + 0x6800)
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/* AHB1 */
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#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)
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#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)
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#define DMAMUX_BASE (PERIPH_BASE_AHB1 + 0x0800)
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#define CORDIC_BASE (PERIPH_BASE_AHB1 + 0x0c00)
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#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)
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#define FMAC_BASE (PERIPH_BASE_AHB1 + 0x1400)
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)
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#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
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/* IO */
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#define GPIO_PORT_A_BASE (PERIPH_BASE_IOPORT + 0x0000)
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#define GPIO_PORT_B_BASE (PERIPH_BASE_IOPORT + 0x0400)
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#define GPIO_PORT_C_BASE (PERIPH_BASE_IOPORT + 0x0800)
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#define GPIO_PORT_D_BASE (PERIPH_BASE_IOPORT + 0x0c00)
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#define GPIO_PORT_E_BASE (PERIPH_BASE_IOPORT + 0x1000)
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#define GPIO_PORT_F_BASE (PERIPH_BASE_IOPORT + 0x1400)
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#define GPIO_PORT_G_BASE (PERIPH_BASE_IOPORT + 0x1800)
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/* AHB2 */
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#define ADC1_BASE (PERIPH_BASE_AHB2 + 0x0000)
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#define ADC2_BASE (ADC1_BASE + 0x0100)
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#define ADC3_BASE (PERIPH_BASE_AHB2 + 0x0400)
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#define ADC4_BASE (ADC3_BASE + 0x0100)
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#define ADC5_BASE (ADC3_BASE + 0x0200)
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#define DAC1_BASE (PERIPH_BASE_AHB2 + 0x0800)
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#define DAC2_BASE (PERIPH_BASE_AHB2 + 0x0c00)
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#define DAC3_BASE (PERIPH_BASE_AHB2 + 0x1000)
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#define DAC4_BASE (PERIPH_BASE_AHB2 + 0x1400)
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#define AES_BASE (PERIPH_BASE_AHB2 + 0x6000)
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#define RNG_BASE (PERIPH_BASE_AHB2 + 0x6800)
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#define FMC_BASE (0xa0000000U)
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#define QUADSPI_BASE (0xa0001000U)
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/* Private peripherals */
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#define DBGMCU_BASE (PPBI_BASE + 0x42000)
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)
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#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)
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#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
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#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
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#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
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#define DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))
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/* ST provided factory calibration values @ 3.0V */
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#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))
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#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))
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#define ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))
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#endif
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