FrancoisFinfe 7b29caed1a stm32l1:rcc: allow pll source to be HSE. ...

The existing rcc_clock_setup_pll only allowed HSI as the clock source, even
though the existing clock structure contains pll source variables.

Check this value, and switch to the corresponding clock source, rather than
blindly assuming that we are tryign to operate from HSI.

2015-07-31 05:21:52 +00:00

..

common

stm32: f24: doxygen updates for flash program width.

2015-07-31 03:51:32 +00:00

f0

make: use shared DEBUG_FLAGS (-gdb3) by default

2015-05-04 13:45:07 +00:00

f1

stm32f1:rtc: whitespace/style cleanup.

2015-07-31 05:21:46 +00:00

f2

make: use shared DEBUG_FLAGS (-gdb3) by default

2015-05-04 13:45:07 +00:00

f3

stm32f3: adc: Add support for sequence completion flags

2015-07-29 13:28:18 +00:00

f4

stm32f4: rcc: Add 84Mhz, max speed for f401

2015-07-31 02:25:23 +00:00

l0

make: use shared DEBUG_FLAGS (-gdb3) by default

2015-05-04 13:45:07 +00:00

l1

stm32l1:rcc: allow pll source to be HSE.

2015-07-31 05:21:52 +00:00

can.c

Stile fixes run, 80 char boundry.

2013-06-12 21:07:35 -07:00

desig.c

[stm32] desig: high nibble to hex char first

2015-01-16 19:12:21 +01:00