253a091936
Merge-conflict: took _prior_ verision of CCS_MUXSELR_MASK_PIN as bracketing of (pin) seemed more correct!
164 lines
6.3 KiB
C
164 lines
6.3 KiB
C
/**
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* @brief Memory Controller definitions for the Qorvo PAC55xx series of microcontrollers
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*
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* @addtogroup PAC55xx_memctl Memory Controller Defines
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* @ingroup PAC55xx_defines
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* @author Kevin Stefanik <kevin@allocor.tech>
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* LGPL License Terms @ref lgpl_license
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* @date 17 Mar 2020
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*
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* Definitions in this file come from the PAC55XX Family User Guide Rev 1.23
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* by Active-Semi dated November 19, 2019.
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020 Kevin Stefanik <kevin@allocor.tech>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PAC55XX_MEMCTL_H_
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#define LIBOPENCM3_PAC55XX_MEMCTL_H_
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/pac55xx/memorymap.h>
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/**@{*/
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/** @defgroup memctl_reg Memory Controller Configuration Register
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@{*/
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/** Memory Controller Configuration Register */
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#define MEMCTL_MEMCTLR MMIO32(MEMCTL_BASE)
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#define MEMCTL_MEMCTLR_WSTATE_MASK (0xF)
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#define MEMCTL_MEMCTLR_WSTATE(ws) ((ws) & MEMCTL_MEMCTLR_WSTATE_MASK)
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#define MEMCTL_MEMCTLR_MCLKDIV_MASK (0xF)
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#define MEMCTL_MEMCTLR_MCLKDIV_SHIFT 4
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/* Supported MCLK divisors: 1-16 */
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#define MEMCTL_MEMCTLR_MCLKDIV(div) (((div-1) & MEMCTL_MEMCTLR_MCLKDIV_MASK) << MEMCTL_MEMCTLR_MCLKDIV_SHIFT)
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#define MEMCTL_MEMCTLR_WRITEWORDCNT_MASK (0x3)
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#define MEMCTL_MEMCTLR_WRITEWORDCNT_SHIFT 8
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#define MEMCTL_MEMCTLR_WRITEWORDCNT(cnt) (((cnt) & MEMCTL_MEMCTLR_WRITEWORDCNT_MASK) << MEMCTL_MEMCTLR_WRITEWORDCNT_SHIFT)
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#define MEMCTL_MEMCTLR_SEIE BIT16
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#define MEMCTL_MEMCTLR_DEIE BIT17
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#define MEMCTL_MEMCTLR_INVADDRIE BIT18
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#define MEMCTL_MEMCTLR_STBY BIT19
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#define MEMCTL_MEMCTLR_ECCDIS BIT20
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#define MEMCTL_MEMCTLR_CACHEDIS BIT21
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#define MEMCTL_MEMCTLR_MCLKSEL BIT22
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/**@}*/
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/** @defgroup memstatus_reg Memory Controller Status Register
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@{*/
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/** Memory Controller Status Register */
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#define MEMCTL_MEMSTATUS MMIO32(MEMCTL_BASE + 0x0004)
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#define MEMCTL_MEMSTATUS_WBUSY BIT0
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#define MEMCTL_MEMSTATUS_EBUSY BIT1
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_MASK (0x3)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_SHIFT 8
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT ((MEMCTL_MEMSTATUS >> MEMCTL_MEMSTATUS_WRITEWORDCNT_SHIFT) & MEMCTL_MEMSTATUS_WRITEWORDCNT_MASK)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_4BYTES (0)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_8BYTES (1)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_12BYTES (2)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_16BYTES (3)
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#define MEMCTL_MEMSTATUS_SE BIT16
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#define MEMCTL_MEMSTATUS_DE BIT17
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#define MEMCTL_MEMSTATUS_INVADDR BIT18
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/**@}*/
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/** @defgroup flashlock_vals Flash Lock/Write Enable Register values
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@{*/
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/** Flash Lock Access Register */
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#define MEMCTL_FLASHLOCK MMIO32(MEMCTL_BASE + 0x0008)
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#define MEMCTL_FLASHLOCK_CLEAR (0)
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#define MEMCTL_FLASHLOCK_ALLOW_FLASH_WRITE (0x43DF140A)
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#define MEMCTL_FLASHLOCK_ALLOW_MEMCTL_WRITE (0xD513B490)
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#define MEMCTL_FLASHLOCK_ALLOW_INFO2_SWDFUSE (0x79B4F762)
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/**@}*/
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/** Flash Page Address Register */
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#define MEMCTL_FLASHPAGE MMIO32(MEMCTL_BASE + 0x000C)
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/** SWD Unlock Register */
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#define MEMCTL_SWDUNLOCK MMIO32(MEMCTL_BASE + 0x0010)
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/** @defgroup flasherase_vals Flash Erase Enable Register values
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@{*/
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/** Flash Erase Enable Register */
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#define MEMCTL_FLASHERASE MMIO32(MEMCTL_BASE + 0x0020)
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#define MEMCTL_FLASHERASE_PAGE_ERASE (0x8C799CA7)
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#define MEMCTL_FLASHERASE_MASS_PAGE_ERASE (0x09EE76C9)
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#define MEMCTL_FLASHERASE_INFO3_ERASE (0x1266FF45)
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/**@}*/
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/**@}*/
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BEGIN_DECLS
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/**
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* @defgroup memctl_api Memory Controller API
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* @ingroup peripheral_apis
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* @brief <b>PAC5xx MEMCTL Driver</b>
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* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
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* @date March 7, 2020
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*
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* This library supports the MEMCTL module in the PAC55xx SoC from Qorvo.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*@{*/
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/** Set the number of wait states for Flash reads.
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* @param[in] wstate Wait states: 0-15
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*/
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void memctl_flash_set_wstate(uint32_t wstate);
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/** Set the MCLK divisor.
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* @param[in] div HCLK to MCLK divisor: 1-16
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*/
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void memctl_flash_set_mclkdiv(uint32_t div);
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/** Set WRITEWORDCOUNT to 0 to reset the Flash write data buffer */
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void memctl_flash_reset_write_buffer(void);
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/** Enable Flash Standby Mode */
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void memctl_flash_standby_mode_enable(void);
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/** Disable Flash Standby Mode */
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void memctl_flash_standby_mode_disable(void);
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/** Enable Flash cache */
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void memctl_flash_cache_enable(void);
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/** Disable Flash cache */
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void memctl_flash_cache_disable(void);
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/** Select ROSCCLK as input to Flash Memory Controller */
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void memctl_flash_select_roscclk(void);
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/** Select MCLK as input to Flash Memory Controller */
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void memctl_flash_select_mclk(void);
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/** Enable SRAM ECC */
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void memctl_sram_ecc_enable(void);
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/** Disable SRAM ECC */
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void memctl_sram_ecc_disable(void);
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/** Enable SRAM ECC Single Bit Detection Interrupt */
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void memctl_sram_ecc_single_bit_interrupt_enable(void);
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/** Disable SRAM ECC Single Bit Detection Interrupt */
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void memctl_sram_ecc_single_bit_interrupt_disable(void);
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/** Enable SRAM ECC Dual Bit Detection Interrupt */
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void memctl_sram_ecc_dual_bit_interrupt_enable(void);
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/** Disable SRAM ECC Dual Bit Detection Interrupt */
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void memctl_sram_ecc_dual_bit_interrupt_disable(void);
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/** Enable Invalid Memory Access Interrupt */
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void memctl_invaddr_interrupt_enable(void);
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/** Disable Invalid Memory Access Interrupt */
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void memctl_invaddr_interrupt_disable(void);
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/**@}*/
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END_DECLS
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#endif /* LIBOPENCM3_PAC55XX_MEMCTL_H_ */
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