libopencm3/scripts/data/lpc43xx/rgu.csv

1	RESET_CTRL0	0	1	CORE_RST	Writing a one activates the reset	0	w
2	RESET_CTRL0	1	1	PERIPH_RST	Writing a one activates the reset	0	w
3	RESET_CTRL0	2	1	MASTER_RST	Writing a one activates the reset	0	w
4	RESET_CTRL0	4	1	WWDT_RST	Writing a one to this bit has no effect	0
5	RESET_CTRL0	5	1	CREG_RST	Writing a one to this bit has no effect	0
6	RESET_CTRL0	8	1	BUS_RST	Writing a one activates the reset	0	w
7	RESET_CTRL0	9	1	SCU_RST	Writing a one activates the reset	0	w
8	RESET_CTRL0	13	1	M4_RST	Writing a one activates the reset	0	w
9	RESET_CTRL0	16	1	LCD_RST	Writing a one activates the reset	0	w
10	RESET_CTRL0	17	1	USB0_RST	Writing a one activates the reset	0	w
11	RESET_CTRL0	18	1	USB1_RST	Writing a one activates the reset	0	w
12	RESET_CTRL0	19	1	DMA_RST	Writing a one activates the reset	0	w
13	RESET_CTRL0	20	1	SDIO_RST	Writing a one activates the reset	0	w
14	RESET_CTRL0	21	1	EMC_RST	Writing a one activates the reset	0	w
15	RESET_CTRL0	22	1	ETHERNET_RST	Writing a one activates the reset	0	w
16	RESET_CTRL0	25	1	FLASHA_RST	Writing a one activates the reset	0	w
17	RESET_CTRL0	27	1	EEPROM_RST	Writing a one activates the reset	0	w
18	RESET_CTRL0	28	1	GPIO_RST	Writing a one activates the reset	0	w
19	RESET_CTRL0	29	1	FLASHB_RST	Writing a one activates the reset	0	w
20	RESET_CTRL1	0	1	TIMER0_RST	Writing a one activates the reset	0	w
21	RESET_CTRL1	1	1	TIMER1_RST	Writing a one activates the reset	0	w
22	RESET_CTRL1	2	1	TIMER2_RST	Writing a one activates the reset	0	w
23	RESET_CTRL1	3	1	TIMER3_RST	Writing a one activates the reset	0	w
24	RESET_CTRL1	4	1	RTIMER_RST	Writing a one activates the reset	0	w
25	RESET_CTRL1	5	1	SCT_RST	Writing a one activates the reset	0	w
26	RESET_CTRL1	6	1	MOTOCONPWM_RST	Writing a one activates the reset	0	w
27	RESET_CTRL1	7	1	QEI_RST	Writing a one activates the reset	0	w
28	RESET_CTRL1	8	1	ADC0_RST	Writing a one activates the reset	0	w
29	RESET_CTRL1	9	1	ADC1_RST	Writing a one activates the reset	0	w
30	RESET_CTRL1	10	1	DAC_RST	Writing a one activates the reset	0	w
31	RESET_CTRL1	12	1	UART0_RST	Writing a one activates the reset	0	w
32	RESET_CTRL1	13	1	UART1_RST	Writing a one activates the reset	0	w
33	RESET_CTRL1	14	1	UART2_RST	Writing a one activates the reset	0	w
34	RESET_CTRL1	15	1	UART3_RST	Writing a one activates the reset	0	w
35	RESET_CTRL1	16	1	I2C0_RST	Writing a one activates the reset	0	w
36	RESET_CTRL1	17	1	I2C1_RST	Writing a one activates the reset	0	w
37	RESET_CTRL1	18	1	SSP0_RST	Writing a one activates the reset	0	w
38	RESET_CTRL1	19	1	SSP1_RST	Writing a one activates the reset	0	w
39	RESET_CTRL1	20	1	I2S_RST	Writing a one activates the reset	0	w
40	RESET_CTRL1	21	1	SPIFI_RST	Writing a one activates the reset	0	w
41	RESET_CTRL1	22	1	CAN1_RST	Writing a one activates the reset	0	w
42	RESET_CTRL1	23	1	CAN0_RST	Writing a one activates the reset	0	w
43	RESET_CTRL1	24	1	M0APP_RST	Writing a one activates the reset	1	w
44	RESET_CTRL1	25	1	SGPIO_RST	Writing a one activates the reset	0	w
45	RESET_CTRL1	26	1	SPI_RST	Writing a one activates the reset	0	w
46	RESET_STATUS0	0	2	CORE_RST	Status of the CORE_RST reset generator output	0x0	rw
47	RESET_STATUS0	2	2	PERIPH_RST	Status of the PERIPH_RST reset generator output	0x0	rw
48	RESET_STATUS0	4	2	MASTER_RST	Status of the MASTER_RST reset generator output	0x1	rw
49	RESET_STATUS0	8	2	WWDT_RST	Status of the WWDT_RST reset generator output	0x0	rw
50	RESET_STATUS0	10	2	CREG_RST	Status of the CREG_RST reset generator output	0x0	rw
51	RESET_STATUS0	16	2	BUS_RST	Status of the BUS_RST reset generator output	0x1	rw
52	RESET_STATUS0	18	2	SCU_RST	Status of the SCU_RST reset generator output	0x1	rw
53	RESET_STATUS0	26	2	M4_RST	Status of the M4_RST reset generator output	0x1	rw
54	RESET_STATUS1	0	2	LCD_RST	Status of the LCD_RST reset generator output	0x1	rw
55	RESET_STATUS1	2	2	USB0_RST	Status of the USB0_RST reset generator output	0x1	rw
56	RESET_STATUS1	4	2	USB1_RST	Status of the USB1_RST reset generator output	0x1	rw
57	RESET_STATUS1	6	2	DMA_RST	Status of the DMA_RST reset generator output	0x1	rw
58	RESET_STATUS1	8	2	SDIO_RST	Status of the SDIO_RST reset generator output	0x1	rw
59	RESET_STATUS1	10	2	EMC_RST	Status of the EMC_RST reset generator output	0x1	rw
60	RESET_STATUS1	12	2	ETHERNET_RST	Status of the ETHERNET_RST reset generator output	0x1	rw
61	RESET_STATUS1	18	2	FLASHA_RST	Status of the FLASHA_RST reset generator output	0x1
62	RESET_STATUS1	22	2	EEPROM_RST	Status of the EEPROM_RST reset generator output	0x1
63	RESET_STATUS1	24	2	GPIO_RST	Status of the GPIO_RST reset generator output	0x1	rw
64	RESET_STATUS1	26	2	FLASHB_RST	Status of the FLASHB_RST reset generator output	0x1	rw
65	RESET_STATUS2	0	2	TIMER0_RST	Status of the TIMER0_RST reset generator output	0x1	rw
66	RESET_STATUS2	2	2	TIMER1_RST	Status of the TIMER1_RST reset generator output	0x1	rw
67	RESET_STATUS2	4	2	TIMER2_RST	Status of the TIMER2_RST reset generator output	0x1	rw
68	RESET_STATUS2	6	2	TIMER3_RST	Status of the TIMER3_RST reset generator output	0x1	rw
69	RESET_STATUS2	8	2	RITIMER_RST	Status of the RITIMER_RST reset generator output	0x1	rw
70	RESET_STATUS2	10	2	SCT_RST	Status of the SCT_RST reset generator output	0x1	rw
71	RESET_STATUS2	12	2	MOTOCONPWM_RST	Status of the MOTOCONPWM_RST reset generator output	0x1	rw
72	RESET_STATUS2	14	2	QEI_RST	Status of the QEI_RST reset generator output	0x1	rw
73	RESET_STATUS2	16	2	ADC0_RST	Status of the ADC0_RST reset generator output	0x1	rw
74	RESET_STATUS2	18	2	ADC1_RST	Status of the ADC1_RST reset generator output	0x1	rw
75	RESET_STATUS2	20	2	DAC_RST	Status of the DAC_RST reset generator output	0x1	rw
76	RESET_STATUS2	24	2	UART0_RST	Status of the UART0_RST reset generator output	0x1	rw
77	RESET_STATUS2	26	2	UART1_RST	Status of the UART1_RST reset generator output	0x1	rw
78	RESET_STATUS2	28	2	UART2_RST	Status of the UART2_RST reset generator output	0x1	rw
79	RESET_STATUS2	30	2	UART3_RST	Status of the UART3_RST reset generator output	0x1	rw
80	RESET_STATUS3	0	2	I2C0_RST	Status of the I2C0_RST reset generator output	0x1	rw
81	RESET_STATUS3	2	2	I2C1_RST	Status of the I2C1_RST reset generator output	0x1	rw
82	RESET_STATUS3	4	2	SSP0_RST	Status of the SSP0_RST reset generator output	0x1	rw
83	RESET_STATUS3	6	2	SSP1_RST	Status of the SSP1_RST reset generator output	0x1	rw
84	RESET_STATUS3	8	2	I2S_RST	Status of the I2S_RST reset generator output	0x1	rw
85	RESET_STATUS3	10	2	SPIFI_RST	Status of the SPIFI_RST reset generator output	0x1	rw
86	RESET_STATUS3	12	2	CAN1_RST	Status of the CAN1_RST reset generator output	0x1	rw
87	RESET_STATUS3	14	2	CAN0_RST	Status of the CAN0_RST reset generator output	0x1	rw
88	RESET_STATUS3	16	2	M0APP_RST	Status of the M0APP_RST reset generator output	0x3	rw
89	RESET_STATUS3	18	2	SGPIO_RST	Status of the SGPIO_RST reset generator output	0x1	rw
90	RESET_STATUS3	20	2	SPI_RST	Status of the SPI_RST reset generator output	0x1	rw
91	RESET_ACTIVE_STATUS0	0	1	CORE_RST	Current status of the CORE_RST	0	r
92	RESET_ACTIVE_STATUS0	1	1	PERIPH_RST	Current status of the PERIPH_RST	0	r
93	RESET_ACTIVE_STATUS0	2	1	MASTER_RST	Current status of the MASTER_RST	0	r
94	RESET_ACTIVE_STATUS0	4	1	WWDT_RST	Current status of the WWDT_RST	0	r
95	RESET_ACTIVE_STATUS0	5	1	CREG_RST	Current status of the CREG_RST	0	r
96	RESET_ACTIVE_STATUS0	8	1	BUS_RST	Current status of the BUS_RST	0	r
97	RESET_ACTIVE_STATUS0	9	1	SCU_RST	Current status of the SCU_RST	0	r
98	RESET_ACTIVE_STATUS0	13	1	M4_RST	Current status of the M4_RST	0	r
99	RESET_ACTIVE_STATUS0	16	1	LCD_RST	Current status of the LCD_RST	0	r
100	RESET_ACTIVE_STATUS0	17	1	USB0_RST	Current status of the USB0_RST	0	r
101	RESET_ACTIVE_STATUS0	18	1	USB1_RST	Current status of the USB1_RST	0	r
102	RESET_ACTIVE_STATUS0	19	1	DMA_RST	Current status of the DMA_RST	0	r
103	RESET_ACTIVE_STATUS0	20	1	SDIO_RST	Current status of the SDIO_RST	0	r
104	RESET_ACTIVE_STATUS0	21	1	EMC_RST	Current status of the EMC_RST	0	r
105	RESET_ACTIVE_STATUS0	22	1	ETHERNET_RST	Current status of the ETHERNET_RST	0	r
106	RESET_ACTIVE_STATUS0	25	1	FLASHA_RST	Current status of the FLASHA_RST	0	r
107	RESET_ACTIVE_STATUS0	27	1	EEPROM_RST	Current status of the EEPROM_RST	0	r
108	RESET_ACTIVE_STATUS0	28	1	GPIO_RST	Current status of the GPIO_RST	0	r
109	RESET_ACTIVE_STATUS0	29	1	FLASHB_RST	Current status of the FLASHB_RST	0	r
110	RESET_ACTIVE_STATUS1	0	1	TIMER0_RST	Current status of the TIMER0_RST	0	r
111	RESET_ACTIVE_STATUS1	1	1	TIMER1_RST	Current status of the TIMER1_RST	0	r
112	RESET_ACTIVE_STATUS1	2	1	TIMER2_RST	Current status of the TIMER2_RST	0	r
113	RESET_ACTIVE_STATUS1	3	1	TIMER3_RST	Current status of the TIMER3_RST	0	r
114	RESET_ACTIVE_STATUS1	4	1	RITIMER_RST	Current status of the RITIMER_RST	0	r
115	RESET_ACTIVE_STATUS1	5	1	SCT_RST	Current status of the SCT_RST	0	r
116	RESET_ACTIVE_STATUS1	6	1	MOTOCONPWM_RST	Current status of the MOTOCONPWM_RST	0	r
117	RESET_ACTIVE_STATUS1	7	1	QEI_RST	Current status of the QEI_RST	0	r
118	RESET_ACTIVE_STATUS1	8	1	ADC0_RST	Current status of the ADC0_RST	0	r
119	RESET_ACTIVE_STATUS1	9	1	ADC1_RST	Current status of the ADC1_RST	0	r
120	RESET_ACTIVE_STATUS1	10	1	DAC_RST	Current status of the DAC_RST	0	r
121	RESET_ACTIVE_STATUS1	12	1	UART0_RST	Current status of the UART0_RST	0	r
122	RESET_ACTIVE_STATUS1	13	1	UART1_RST	Current status of the UART1_RST	0	r
123	RESET_ACTIVE_STATUS1	14	1	UART2_RST	Current status of the UART2_RST	0	r
124	RESET_ACTIVE_STATUS1	15	1	UART3_RST	Current status of the UART3_RST	0	r
125	RESET_ACTIVE_STATUS1	16	1	I2C0_RST	Current status of the I2C0_RST	0	r
126	RESET_ACTIVE_STATUS1	17	1	I2C1_RST	Current status of the I2C1_RST	0	r
127	RESET_ACTIVE_STATUS1	18	1	SSP0_RST	Current status of the SSP0_RST	0	r
128	RESET_ACTIVE_STATUS1	19	1	SSP1_RST	Current status of the SSP1_RST	0	r
129	RESET_ACTIVE_STATUS1	20	1	I2S_RST	Current status of the I2S_RST	0	r
130	RESET_ACTIVE_STATUS1	21	1	SPIFI_RST	Current status of the SPIFI_RST	0	r
131	RESET_ACTIVE_STATUS1	22	1	CAN1_RST	Current status of the CAN1_RST	0	r
132	RESET_ACTIVE_STATUS1	23	1	CAN0_RST	Current status of the CAN0_RST	0	r
133	RESET_ACTIVE_STATUS1	24	1	M0APP_RST	Current status of the M0APP_RST	0	r
134	RESET_ACTIVE_STATUS1	25	1	SGPIO_RST	Current status of the SGPIO_RST	0	r
135	RESET_ACTIVE_STATUS1	26	1	SPI_RST	Current status of the SPI_RST	0	r
136	RESET_EXT_STAT0	0	1	EXT_RESET	Reset activated by external reset from reset pin	0	rw
137	RESET_EXT_STAT0	4	1	BOD_RESET	Reset activated by BOD reset	0	rw
138	RESET_EXT_STAT0	5	1	WWDT_RESET	Reset activated by WWDT time-out	0	rw
139	RESET_EXT_STAT1	1	1	CORE_RESET	Reset activated by CORE_RST output	0	rw
140	RESET_EXT_STAT2	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
141	RESET_EXT_STAT4	1	1	CORE_RESET	Reset activated by CORE_RST output	0	rw
142	RESET_EXT_STAT5	1	1	CORE_RESET	Reset activated by CORE_RST output	0	rw
143	RESET_EXT_STAT8	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
144	RESET_EXT_STAT9	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
145	RESET_EXT_STAT13	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
146	RESET_EXT_STAT16	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
147	RESET_EXT_STAT17	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
148	RESET_EXT_STAT18	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
149	RESET_EXT_STAT19	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
150	RESET_EXT_STAT20	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
151	RESET_EXT_STAT21	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
152	RESET_EXT_STAT22	3	1	MASTER_RESET	Reset activated by MASTER_RST output	0	rw
153	RESET_EXT_STAT25	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
154	RESET_EXT_STAT27	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
155	RESET_EXT_STAT28	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
156	RESET_EXT_STAT29	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
157	RESET_EXT_STAT32	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
158	RESET_EXT_STAT33	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
159	RESET_EXT_STAT34	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
160	RESET_EXT_STAT35	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
161	RESET_EXT_STAT36	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
162	RESET_EXT_STAT37	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
163	RESET_EXT_STAT38	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
164	RESET_EXT_STAT39	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
165	RESET_EXT_STAT40	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
166	RESET_EXT_STAT41	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
167	RESET_EXT_STAT42	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
168	RESET_EXT_STAT44	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
169	RESET_EXT_STAT45	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
170	RESET_EXT_STAT46	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
171	RESET_EXT_STAT47	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
172	RESET_EXT_STAT48	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
173	RESET_EXT_STAT49	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
174	RESET_EXT_STAT50	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
175	RESET_EXT_STAT51	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
176	RESET_EXT_STAT52	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
177	RESET_EXT_STAT53	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
178	RESET_EXT_STAT54	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
179	RESET_EXT_STAT55	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
180	RESET_EXT_STAT56	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output		rw
181	RESET_EXT_STAT57	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw
182	RESET_EXT_STAT58	2	1	PERIPHERAL_RESET	Reset activated by PERIPHERAL_RST output	0	rw