227 lines
11 KiB
C
227 lines
11 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* .. based on file from F4.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- STM32 specific peripheral definitions ------------------------------- */
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/* Memory map for all buses */
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#define FLASH_BASE (0x08000000U)
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/* Non-secure */
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#define PERIPH_BASE_NS (0x40000000U)
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/* Secure, non-secure callable*/
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#define PERIPH_BASE_SC (0x50000000U)
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#define PERIPH_BASE PERIPH_BASE_NS
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000000U)
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#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x00012C00U)
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#define PERIPH_BASE_APB3 (PERIPH_BASE + 0x06000400U)
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#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000U)
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#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x02020000U)
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#define PERIPH_BASE_AHB3 (PERIPH_BASE + 0x06020000U)
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/* Register boundary addresses */
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000U)
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#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400U)
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#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800U)
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#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0C00U)
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000U)
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#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400U)
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/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 2BFF): Reserved */
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2C00U)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000U)
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/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
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#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800U)
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/* PERIPH_BASE_APB1 + 0x3C00 (0x4000 3C00 - 0x4000 43FF): Reserved */
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400U)
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#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800U)
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#define USART4_BASE (PERIPH_BASE_APB1 + 0x4C00U)
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#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000U)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400U)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800U)
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/* PERIPH_BASE_APB1 + 0x5C00 (0x4000 5C00 - 0x4000 5FFF): Reserved */
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#define CRS_BASE (PERIPH_BASE_APB1 + 0x6000U)
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#define USART6_BASE (PERIPH_BASE_APB1 + 0x6400U)
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/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 83FF): Reserved */
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#define I2C4_BASE (PERIPH_BASE_AHB1 + 0x8500U)
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/* PERIPH_BASE_APB1 + 0x8800 (0x4000 8800 - 0x4000 93FF): Reserved */
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#define LPTIM2_BASE (PERIPH_BASE_AHB1 + 0x9400U)
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#define I2C5_BASE (PERIPH_BASE_AHB1 + 0x9800U)
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#define I2C6_BASE (PERIPH_BASE_AHB1 + 0x9C00U)
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/* PERIPH_BASE_APB1 + 0xA000 (0x4000 A000 - 0x4000 A3FF): Reserved */
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#define FDCAN1_BASE (PERIPH_BASE_AHB1 + 0xA400U)
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/* PERIPH_BASE_APB1 + 0xA800 (0x4000 A800 - 0x4000 ABFF): Reserved */
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#define FDCAN1_RAM_BASE (PERIPH_BASE_AHB1 + 0xAC00U)
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/* PERIPH_BASE_APB1 + 0xB000 (0x4000 B000 - 0x4000 DBFF): Reserved */
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#define UCPD1_BASE (PERIPH_BASE_AHB1 + 0xDC00U)
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/* PERIPH_BASE_APB1 + 0xE000 (0x4000 E000 - 0x4000 2BFF): Reserved */
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/* APB2 */
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#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000U)
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x0400U)
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#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0800U)
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x0C00U)
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/* PERIPH_BASE_APB2 + 0x1000 (0x4001 3C00 - 0x4001 3FFF): Reserved */
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#define TIM15_BASE (PERIPH_BASE_APB2 + 0x1400U)
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#define TIM16_BASE (PERIPH_BASE_APB2 + 0x1800U)
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#define TIM17_BASE (PERIPH_BASE_APB2 + 0x1C00U)
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/* PERIPH_BASE_APB2 + 0x2000 (0x4001 4C00 - 0x4001 53FF): Reserved */
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#define SAI1_BASE (PERIPH_BASE_APB2 + 0x2800U)
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#define SAI2_BASE (PERIPH_BASE_APB2 + 0x2C00U)
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/* PERIPH_BASE_APB2 + 0x3000 (0x4001 5C00 - 0x4001 5FFF): Reserved */
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#define USB_BASE (PERIPH_BASE_APB2 + 0x3400U)
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#define USB_RAM_BASE (PERIPH_BASE_APB2 + 0x3800U)
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#define GFXTIM_BASE (PERIPH_BASE_APB2 + 0x3800U)
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#define LTDC_BASE (PERIPH_BASE_APB2 + 0x3C00U)
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#define DSI_BASE (PERIPH_BASE_APB2 + 0x4000U)
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/* PERIPH_BASE_APB2 + 0x5000 (0x4001 7C00 - 0x4001 FFFF): Reserved */
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/* AHB1 */
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#define GPDMA1_BASE (PERIPH_BASE_AHB1 + 0x0000U)
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#define CORDIC_BASE (PERIPH_BASE_AHB1 + 0x1000U)
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#define FMAC_BASE (PERIPH_BASE_AHB1 + 0x1400U)
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/* PERIPH_BASE_AHB1 + 0x1800 (0x4002 1800 - 0x4002 1FFF): Reserved */
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000U)
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/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */
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#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000U)
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/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 3FFF): Reserved */
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#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000U)
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/* PERIPH_BASE_AHB1 + 0x4400 (0x4002 4400 - 0x4002 4FFF): Reserved */
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#define MDF1_BASE (PERIPH_BASE_AHB1 + 0x5000U)
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#define RAMCFG_BASE (PERIPH_BASE_AHB1 + 0x6000U)
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/* PERIPH_BASE_AHB1 + 0x7000 (0x4002 7000 - 0x4002 AFFF): Reserved */
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#define JPEG_BASE (PERIPH_BASE_AHB1 + 0xA000U)
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#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U)
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/* PERIPH_BASE_AHB1 + 0xBC00 (0x4002 BC00 - 0x4002 BFFF): Reserved */
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#define GFXMMU_BASE (PERIPH_BASE_AHB1 + 0xC000U)
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#define GPU2D_BASE (PERIPH_BASE_AHB1 + 0xF000U)
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/* PERIPH_BASE_AHB1 + 0x10000 (0x4003 0000 - 0x4003 03FF): Reserved */
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#define ICACHE_BASE (PERIPH_BASE_AHB1 + 0x10400U)
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/* PERIPH_BASE_AHB1 + 0x10800 (0x4003 0800 - 0x4003 13FF): Reserved */
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#define DCACHE1_BASE (PERIPH_BASE_AHB1 + 0x11400U)
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#define DCACHE2_BASE (PERIPH_BASE_AHB1 + 0x11800U)
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/* PERIPH_BASE_AHB1 + 0x11C00 (0x4003 1C00 - 0x4003 23FF): Reserved */
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#define GTZC1_TZSC_BASE (PERIPH_BASE_AHB1 + 0x12400U)
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#define GTZC1_TZIC_BASE (PERIPH_BASE_AHB1 + 0x12800U)
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#define GTZC1_MPCBB1_BASE (PERIPH_BASE_AHB1 + 0x12C00U)
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#define GTZC1_MPCBB2_BASE (PERIPH_BASE_AHB1 + 0x13000U)
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#define GTZC1_MPCBB3_BASE (PERIPH_BASE_AHB1 + 0x13400U)
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#define GTZC1_MPCBB5_BASE (PERIPH_BASE_AHB1 + 0x13C00U)
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#define GTZC1_MPCBB6_BASE (PERIPH_BASE_AHB1 + 0x13800U)
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/* PERIPH_BASE_AHB1 + 0x14000 (0x4003 4000 - 0x4003 63FF): Reserved */
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#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x16400U)
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/* PERIPH_BASE_AHB1 + 0x16C00 (0x4003 6C00 - 0x4201 FFFF): Reserved */
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/* AHB2 */
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#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000U)
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#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400U)
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#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800U)
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#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00U)
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#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000U)
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#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400U)
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#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800U)
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#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1C00U)
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#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB2 + 0x2000U)
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#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB2 + 0x2400U)
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/* PERIPH_BASE_AHB2 + 0x2800 (0x4202 2800 - 0x4202 7FFF): Reserved */
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#define ADC1_BASE (PERIPH_BASE_AHB2 + 0x8000U)
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/* PERIPH_BASE_AHB2 + 0x8400 (0x4202 8400 - 0x4202 BFFF): Reserved */
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#define DCMI_BASE (PERIPH_BASE_AHB2 + 0xC000U)
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#define PSSI_BASE (PERIPH_BASE_AHB2 + 0xC400U)
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/* PERIPH_BASE_AHB2 + 0xC800 (0x4202 C800 - 0x4203 FFFF): Reserved */
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#define OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x20000U)
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#define OTG_HS_BASE (PERIPH_BASE_AHB2 + 0x20000U)
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#define AES_BASE (PERIPH_BASE_AHB2 + 0xA0000U)
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#define HASH_BASE (PERIPH_BASE_AHB2 + 0xA0400U)
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#define RNG_BASE (PERIPH_BASE_AHB2 + 0xA0800U)
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#define SAES_BASE (PERIPH_BASE_AHB2 + 0xA0C00U)
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/* PERIPH_BASE_AHB2 + 0xA1000 (0x420C 1000 - 0x420C 1FFF): Reserved */
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#define PKA_BASE (PERIPH_BASE_AHB2 + 0xA2000U)
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#define OCTOSPIM_BASE (PERIPH_BASE_AHB2 + 0xA4000U)
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/* PERIPH_BASE_AHB2 + 0xA4400 (0x420C 4400 - 0x420C 4FFF): Reserved */
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#define OTFDEC1_BASE (PERIPH_BASE_AHB2 + 0xA5000U)
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#define OTFDEC2_BASE (PERIPH_BASE_AHB2 + 0xA5400U)
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/* PERIPH_BASE_AHB2 + 0xA5800 (0x420C 5800 - 0x420C 7FFF): Reserved */
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#define SDMMC1_BASE (PERIPH_BASE_AHB2 + 0xA8000U)
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#define DLYBSD1_BASE (PERIPH_BASE_AHB2 + 0xA8400U)
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#define DLYBSD2_BASE (PERIPH_BASE_AHB2 + 0xA8800U)
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#define SDMMC2_BASE (PERIPH_BASE_AHB2 + 0xA8C00U)
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/* PERIPH_BASE_AHB2 + 0xA9000 (0x420C 9000 - 0x420C EFFF): Reserved */
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#define DLYBOS1_BASE (PERIPH_BASE_AHB2 + 0xAF000U)
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#define DLYBOS2_BASE (PERIPH_BASE_AHB2 + 0xAF400U)
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/* PERIPH_BASE_AHB2 + 0xAF800 (0x420C F800 - 0x420D 03FF): Reserved */
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#define FSMC_BASE (PERIPH_BASE_AHB2 + 0xB0400U)
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/* PERIPH_BASE_AHB2 + 0xB0800 (0x420D 0800 - 0x420D 13FF): Reserved */
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#define OCTOSPI1_BASE (PERIPH_BASE_AHB2 + 0xB1400U)
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/* PERIPH_BASE_AHB2 + 0xB1800 (0x420D 1800 - 0x420D 23FF): Reserved */
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#define OCTOSPI2_BASE (PERIPH_BASE_AHB2 + 0xB2400U)
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/* PERIPH_BASE_AHB2 + 0xB2800 (0x420D 2800 - 0x420D 33FF): Reserved */
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#define HSPI1_BASE (PERIPH_BASE_AHB2 + 0xB3400U)
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/* PERIPH_BASE_AHB2 + 0xB3800 (0x420D 3800 - 0x4600 03FF): Reserved */
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/* APB3 */
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#define SYSCFG_BASE (PERIPH_BASE_APB3 + 0x0000U)
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/* PERIPH_BASE_APB3 + 0x0400 (0x4600 0800 - 0x4600 1FFF): Reserved */
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#define SPI3_BASE (PERIPH_BASE_APB3 + 0x1C00U)
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#define LPUART1_BASE (PERIPH_BASE_APB3 + 0x2000U)
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#define I2C3_BASE (PERIPH_BASE_APB3 + 0x2400U)
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/* PERIPH_BASE_APB3 + 0x2800 (0x4600 2C00 - 0x4600 43FF): Reserved */
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#define LPTIM1_BASE (PERIPH_BASE_APB3 + 0x4000U)
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#define LPTIM3_BASE (PERIPH_BASE_APB3 + 0x4400U)
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#define LPTIM_BASE (PERIPH_BASE_APB3 + 0x4800U)
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#define OPAMP_BASE (PERIPH_BASE_APB3 + 0x4C00U)
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#define COMP_BASE (PERIPH_BASE_APB3 + 0x5000U)
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/* PERIPH_BASE_APB3 + 0x5400 (0x4600 5800 - 0x4600 73FF): Reserved */
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#define VREFBUF_BASE (PERIPH_BASE_APB3 + 0x7000U)
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#define RTC_BASE (PERIPH_BASE_APB3 + 0x7400U)
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#define TAMP_BASE (PERIPH_BASE_APB3 + 0x7800U)
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/* PERIPH_BASE_APB3 + 0x7C00 (0x4600 8000 - 0x4601 FFFF): Reserved */
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/* AHB3 */
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#define LPGPIO1_BASE (PERIPH_BASE_AHB3 + 0x0000U)
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/* PERIPH_BASE_AHB3 + 0x0400 (0x4602 0400 - 0x4602 07FF): Reserved */
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#define PWR_BASE (PERIPH_BASE_AHB3 + 0x0800U)
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#define RCC_BASE (PERIPH_BASE_AHB3 + 0x0C00U)
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#define ADC4_BASE (PERIPH_BASE_AHB3 + 0x1000U)
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/* PERIPH_BASE_AHB3 + 0x1400 (0x4602 1400 - 0x4602 17FF): Reserved */
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#define DAC1_BASE (PERIPH_BASE_AHB3 + 0x1800U)
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/* PERIPH_BASE_AHB3 + 0x1C00 (0x4602 1C00 - 0x4602 1FFF): Reserved */
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#define EXTI_BASE (PERIPH_BASE_AHB3 + 0x2000U)
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/* PERIPH_BASE_AHB3 + 0x2400 (0x4602 2400 - 0x4602 2FFF): Reserved */
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#define GTZC2_TZSC_BASE (PERIPH_BASE_AHB3 + 0x3000U)
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#define GTZC2_TZIC_BASE (PERIPH_BASE_AHB3 + 0x3400U)
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#define GTZC2_MPCBB4_BASE (PERIPH_BASE_AHB3 + 0x3800U)
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/* PERIPH_BASE_AHB3 + 0x3C00 (0x4602 3C00 - 0x4602 3FFF): Reserved */
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#define ADF1_BASE (PERIPH_BASE_AHB3 + 0x4000U)
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#define LPDMA1_BASE (PERIPH_BASE_AHB3 + 0x5000U)
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/* PERIPH_BASE_AHB3 + 0x6000 (0x4602 6000 - 0x4FFF FFFF): Reserved */
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#endif
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