66bf499e1b
This commit adds support for NRF52 TWI Master mode and slightly extends existing I2C API. This is a breaking change, while mode selection needs to be done during enabling I2C. There is one additional breaking change done because: 1) Unicore MX API design was PITA for writes 2) It is incompatible with EasyDMA I strongly apologize to all two users who might be affected by this change.
163 lines
5.0 KiB
C
163 lines
5.0 KiB
C
/** @addtogroup i2c_defines
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*
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* @author @htmlonly © @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
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* @author @htmlonly © @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
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*
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**/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
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* Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/nrf/memorymap.h>
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#include <libopencm3/nrf/periph.h>
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/**@{*/
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/* I2C bus */
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/** @addtogroup i2c_block I2C instances
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* @{
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*/
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#define I2C0 I2C0_BASE
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#define I2C1 I2C1_BASE
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/**@}*/
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/* Tasks */
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#define I2C_TASK_STARTRX(i2c) MMIO32((i2c) + 0x000)
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#define I2C_TASK_STARTTX(i2c) MMIO32((i2c) + 0x008)
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#define I2C_TASK_STOP(i2c) MMIO32((i2c) + 0x014)
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#define I2C_TASK_SUSPEND(i2c) MMIO32((i2c) + 0x01c)
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#define I2C_TASK_RESUME(i2c) MMIO32((i2c) + 0x020)
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/* Events */
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#define I2C_EVENT_STOPPED(i2c) MMIO32((i2c) + 0x104)
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#define I2C_EVENT_RXDREADY(i2c) MMIO32((i2c) + 0x108)
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#define I2C_EVENT_TXDSENT(i2c) MMIO32((i2c) + 0x11c)
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#define I2C_EVENT_ERROR(i2c) MMIO32((i2c) + 0x124)
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#define I2C_EVENT_BB(i2c) MMIO32((i2c) + 0x138)
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#define I2C_EVENT_SUSPENDED(i2c) MMIO32((i2c) + 0x148)
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/* Registers */
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#define I2C_SHORTS(i2c) MMIO32((i2c) + 0x200)
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#define I2C_INTEN(i2c) MMIO32((i2c) + 0x300)
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#define I2C_INTENSET(i2c) MMIO32((i2c) + 0x304)
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#define I2C_INTENCLR(i2c) MMIO32((i2c) + 0x308)
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#define I2C_ERRORSRC(i2c) MMIO32((i2c) + 0x4c4)
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#define I2C_ENABLE(i2c) MMIO32((i2c) + 0x500)
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#define I2C_PSELSCL(i2c) MMIO32((i2c) + 0x508)
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#define I2C_PSELSDA(i2c) MMIO32((i2c) + 0x50c)
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#define I2C_RXD(i2c) MMIO32((i2c) + 0x518)
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#define I2C_TXD(i2c) MMIO32((i2c) + 0x51c)
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#define I2C_FREQUENCY(i2c) MMIO32((i2c) + 0x524)
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#define I2C_ADDRESS(i2c) MMIO32((i2c) + 0x588)
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/* Register Contents */
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/** @addtogroup i2c_shorts I2C event -> task shortcuts
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* The effect of activated shortcut is, that upon I2C event
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* triggering, the hardware will automatically start chosen
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* task without intervention of the software.
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* @{
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*/
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/** On byte boundary, activate suspend task. */
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#define I2C_SHORTS_BB_SUSPEND (1 << 0)
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/** On byte boundary, activate stop task. */
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#define I2C_SHORTS_BB_STOP (1 << 1)
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/**@}*/
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/** @addtogroup i2c_interrupts I2C interrupts
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* @{
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*/
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#define I2C_INTEN_STOPPED (1 << 1)
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#define I2C_INTEN_RXDREADY (1 << 2)
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#define I2C_INTEN_TXDSENT (1 << 7)
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#define I2C_INTEN_ERROR (1 << 9)
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#define I2C_INTEN_BB (1 << 14)
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/**@}*/
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#define I2C_ERRORSRC_OVERRUN (1 << 0)
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#define I2C_ERRORSRC_ANACK (1 << 1)
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#define I2C_ERRORSRC_DNACK (1 << 2)
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/** @addtogroup i2c_mode I2C peripheral mode
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* @{
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*/
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/** NRF51 legacy mode.
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* On NRF51, this is the only mode available.
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* On NRF52, this mode does not support EasyDMA.
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*/
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#define I2C_MODE_LEGACY (5)
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/**@}*/
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/** @addtogroup i2c_freq_const I2C frequency constants
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* @{
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*/
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/** 100kHz */
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#define I2C_FREQUENCY_100K (0x01980000)
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/** 250kHz */
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#define I2C_FREQUENCY_250K (0x04000000)
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/** 390kHz
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* @note: This value is not documented in datasheet. It provides
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* ~390kHz clock with correct timing.
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*/
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#define I2C_FREQUENCY_390K (0x06200000)
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/** 400kHz
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* @note: According to datasheet, there is HW bug which prevents
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* MCU from generating correct timings, therefore it might be
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* unusable. Use @ref I2C_FREQUENCY_390K instead, if this affects
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* you.
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*/
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#define I2C_FREQUENCY_400K (0x06680000)
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/**@}*/
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#define I2C_PSEL_OFF (0xffffffff)
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/**@}*/
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BEGIN_DECLS
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void i2c_enable(uint32_t i2c, uint32_t mode);
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void i2c_disable(uint32_t i2c);
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void i2c_start_tx(uint32_t i2c);
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void i2c_start_rx(uint32_t i2c);
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void i2c_send_stop(uint32_t i2c);
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void i2c_set_fast_mode(uint32_t i2c);
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void i2c_set_standard_mode(uint32_t i2c);
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void i2c_set_frequency(uint32_t i2c, uint32_t freq);
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void i2c_send_data(uint32_t i2c, uint8_t data);
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uint8_t i2c_get_data(uint32_t i2c);
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void i2c_select_pins(uint32_t i2c, uint32_t scl_pin, uint32_t sda_pin);
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void i2c_set_address(uint32_t i2c, uint8_t addr);
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void i2c_resume(uint32_t i2c);
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void i2c_set_shorts(uint32_t i2c, uint32_t shorts);
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END_DECLS
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